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A growing number of semiconductor applications are turning to 2.5D and 3D integration. Integrating multiple dies in a single package can reduce total power consumption, reduce required PCB area, enhance performance and it can speed up development cycles.

It is important to consider Electrostatic Discharge (ESD) protection early in the design phase. The 2.5D and 3D hybrid integration introduces new ESD challenges but also opportunities.

Custom ESD requirements

Die-2-die interfaces can benefit from custom ESD solutions.

High-speed communication between chiplets require I/Os and ESD protection with low parasitic capacitance

Chiplets manufactured on the most advanced FinFET processes need effective ESD protection clamps to safeguard the sensitive circuits

Chiplet interfaces can operate at a low signal voltage like 1V or lower, below the voltage of conventional I/O’s.

Sofics IP for chiplets, die-2-die interfaces

Key focus areas

A. High-Speed interfaces

Sofics IP is already used for many high-speed die-2-die interfaces.  These interfaces need ESD clamps with low parasitic capacitance. Sofics clamps provide standard ESD robustness and do not require a resistance in the signal path.

B. Scalable ESD robustness

Connections between different dies in an 3D assembly are not exposed once the IC package is sealed. Moreover, the assembly is typically performed under very (ESD) safe/controlled conditions. The ESD robustness requirement can be drastically reduced. Sofics ESD cells are easily scaled.

C. Low voltage signaling

Die-2-die interfaces can operate at lower voltages, below the standard I/O voltage and can be designed with thin oxide transistors. Sofics has delivered ESD protection solutions for the most sensitive transistors on CMOS and FinFET processes and operating at a voltage of 1V or lower.

D. Sensitive circuits

Chiplet interfaces built using thin oxide transistors are very sensitive to ESD stress. It is imperative to use fast, local ESD clamps to limit the voltage drop during fast ESD transients.

Process technology covered

Mature CMOS (0.5um to 180nm)

Mainstream CMOS (130nm to 65nm)

Advanced CMOS (40nm to 22nm)

FinFET technology

BiCMOS technology

Foundries covered



IC products from our customers

Sofics ESD protection has been used by several leading fabless companies to protect chiplet interfaces. We supported 15+ projects in silicon photonics where optical and electrical dies are combined in a single module. Our IP is also used for AI chips that employ optical connections between memory and compute.

Related applications

Automotive Electronics

Wired, wireless, optical comm.

Data center

Internet of Things