Local clamp

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Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology

Sofics' 2021 IEDS publication. Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
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Selecting optimized ESD protection for CMOS image sensors

Today, you can find CMOS image sensors almost everywhere in consumer, automotive, health and security applications. There has been a lot of innovation to enable demanding requirements. The article provides a summary about the 3 main aspects that IC designers need to consider when selecting the ESD protection clamps for their image sensor projects.
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3 approaches to handle EOS ‘requirements’

EOS, or Electrical Overstress, is any electrical stress that exceeds any of the specified absolute maximum ratings (AMR) of a product. It is important to discuss because many products are damaged this way. This article includes case studies and 3 approaches to handle those requests.
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Optimized on-chip ESD protection to enable high-speed Ethernet in cars.

In the past most Electronic Control Units (ECU) used CAN and LIN interfaces to connect to sensors, actuators and each other. However, the newest applications need (much) faster communication options. Gigabit automotive ethernet is pushed by many in the industry as the perfect solution. With its local ESD clamp approach, Sofics provides the best solution[...]
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Optimized ESD protection based on Silicon Controlled Rectifiers (SCR), verified on Samsung Foundry 4nm and 8nm FinFET processes

Engineers developing semiconductor devices in the most advanced FinFET technology need improved ESD protection solutions. We demonstrate ESD protection solutions based on proprietary Silicon Controlled Rectifiers verified on the Samsung Foundry 8nm and 4nm FinFET process.
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Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology

Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.
Read More