• Custom designs
    for high robustness

  • IO and ESD integrated solutions

  • Higher voltage rated IO's

  • Proven designs down to 28nm

  • Sofics' development or in collaboration with design partner

  • Low design cost

  • Allow your team to focus on core circuit development

  • Customized and optimized per applications

  • Low wafer cost

  • Smaller silicon footprint

  • Time-to-market

  • First time right

  • Easy access to support engineers

  • Risk reduction

  • Leveraging design-for-robustness expertise

  • Clean IP portfolio

  • Circuit design
    with integrated robustness

  • Leveraged from TakeCharge and PowerQubic

  • Any specification, any disturbance

  • Circuit design
    for higher robustness

  • Clipping circuit to protect IO
    from high voltages


  • Higher voltage rated IO's
    for advanced processes

  • 3.0V with 1.8V transistors

  • Product proven in TSMC 40nm and 28nm

  • in collaboration with ICSense

  • Clipping circuit
    for antenna applications

  • Multiple modes of operation

  • Low leakage


  • Product proven in TSMC 55nm:

  • Programmable clipping at 2.2V, 3.3V and no clipping