Protect IC interfaces against Electrostatic Discharge

Sofics offers the semiconductor industry's most advanced technology for protecting against electrostatic discharge and electrical overstress (ESD/EOS) in ICs.

TakeCharge on-chip ESD protection up to 5V interfaces

When generic or foundry on-chip solutions for ESD do not meet your needs, TakeCharge® technology is the logical choice. Proven in thousands of ICs in commercial production, it offers a fast, reliable way to balance ESD protection with cost while enabling maximum IC performance.

Technical benefits

  • Low parasitic capacitance for high speed or wireless interface protection: 100fF or lower
  • Low leakage for analog interface protection
  • Protect interfaces with most sensitive nodes like thin gates, core devices

Available

  • Customized EOS/ESD solutions can be delivered within a few weeks for almost any CMOS node
  • Proven in more than 50 foundry and proprietary technologies
  • Reduce time to market by several months

Cost-efficient

  • Silicon and product proven ESD solutions help to reduce IC development costs
  • Smaller silicon footprint – reduce production cost by 1 to 10% through smaller dies
  • Compatible with standard process flow – e.g. possible to skip ESD implant mask/step and save about 40$/wafer

PowerQubic on-chip ESD protection for 5V to 100V interfaces

Sofics engineers developed revolutionary on-chip ESD devices to protect interfaces up to 80V against EOS/ESD. PowerQubic is immune to latch-up and electrical overstress.

Technical benefits

  • Customizable protection: easily adapt for a broad set of reliability and functional requirements
  • Protect against most severe specifications like IEC 61000-4-2, ISO 7637-2, transient latch-up, ...
  • Small silicon footprint, compatible with standard process flow

Available

  • Customized EOS/ESD solutions can be delivered within a few weeks for TSMC 0.25 and 0.18um BCD technologies
  • Concepts proven in advanced CMOS (65nm, 28nm)
  • Proven in several projects and applications

Cost-efficient

  • Silicon and product proven ESD solutions – reduce development cost.
  • Smaller silicon footprint – reduce production cost by 1 to 10%
  • Compatible with standard process flow

CustomIO High-performance Non-standard I/Os

Robust, integrated specialty ESD, most efficient development path.

Today’s IC designs often call for non-standard interface performance. Sometimes the required I/O solution is not available for download and the ESD design rules do not support your target IC application. CustomIO from Sofics is the answer. Under this program we partner with designers of specialty I/Os to create solutions that combine exceptional I/O performance with robust ESD protection.

Together with ICsense we developed an I/O with integrated ESD protection for Icera (Now Nvidia) in TSMC 40nm and 28nm.

Customer quotes:
true 3.3V signaling without the extra cost of 2.5V/3.3V masks safely handle off-chip interfaces up to 3.6 volts with 1.8-volt internal transistors The design worked right the first time

ESDdoctor Debug ESD related problems

When standard electrostatic discharge and electrical overstress (ESD/EOS) solutions aren’t enough to protect your IC or SOC, call on expert help to fix the problem and get your product on its way to the market. Our ESDdoctor consulting service can identify, diagnose, and solve any ESD/EOS problem quickly and definitively, at a surprisingly low entry cost. You can choose testing and diagnosis only, or add ESD design services to the consulting package.

ESD, Latch-up testing

  • HBM (ANSI/ESDA and JEDEC) on packaged dies
  • MM (ANSI/ESDA and JEDEC) on packaged dies
  • Latch-up JEDEC on packaged dies TLP on packaged and bare dies
  • VF-TLP on bare dies
  • Solid state pulsing on packaged and bare dies
  • IEC 61000-4-2 gun testing DC leakage and IV tracing on packaged and bare dies
  • Thermo chuck up to 200°C
  • Test boards and sockets for various packages

Design service

  • Sofics helps customers identify the best full-chip ESD solution for their needs. We examine and combine public, customer-developed, and Sofics proprietary solutions as necessary. The result will be in full conformity with foundry-supplied guidelines.
  • In spite of its low threshold for entry, this service leverages our extensive experience in providing product- proven ESD solutions through 9 consecutive CMOS generations (0.5um down to 28nm) in all leading foundries.

Find out how Sofics can support your application.

Provide us some information about your current project and receive our reply shortly.