FinFET

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Protecting chip interfaces in FinFET nodes against Electrostatic Discharge (ESD) needs dedicated attention. ESD remains an important reliability issue for semiconductor companies. ESD events can occur during several stages in the development, assembly and actual use of the ICs.

Sofics has verified its ESD protection clamps on 9 different FinFET process nodes at TSMC and Samsung Foundry. Integrating our solutions can enhance your competitive advantage.

Why FinFET designs require custom ESD cells

There are 3 reasons why ESD solutions on FinFET technology is challenging

Basic building blocks like FinFET transistors are very sensitive to ESD stress.

Traditional ESD approaches are no longer effective.

The design complexity has increased a lot.

Moreover, the foundry provided General Purpose I/O libraries introduce contraints. For instance the voltage range of the I/O libraries prevents communication with legacy chips running at 3V or higher. The parasitic capacitance of the integrated ESD protection clamps is too high for interfaces running at speeds beyond 10 Gbps. The leakage current of traditional ESD clamps prevents low-power applications.

Why FinFET designs require custom ESD cells

There are 3 reasons why ESD solutions on FinFET technology is challenging

Basic building blocks like FinFET transistors are very sensitive to ESD stress.

Traditional ESD approaches are no longer effective.

The design complexity has increased a lot.

Moreover, the foundry provided General Purpose I/O libraries introduce contraints. For instance the voltage range of the I/O libraries prevents communication with legacy chips running at 3V or higher. The parasitic capacitance of the integrated ESD protection clamps is too high for interfaces running at speeds beyond 10 Gbps. The leakage current of traditional ESD clamps prevents low-power applications.

Sofics IP for FinFET technology

Process technology covered

TSMC 16nm

TSMC 12nm

TSMC 7nm

TSMC 6nm

TSMC 5nm

TSMC 3nm MPW planned

Samsung Foundry 14nm

Samsung Foundry 8nm

Samsung Foundry 5nm

Samsung Foundry 4nm

Foundries covered

Key focus areas

A. High-Speed interfaces

Sofics IP on FinFET is used in high bandwidth communication interfaces for wired and optical networks including 28Gbps, 56Gbps and 112Gbps SerDes. These interfaces need ESD clamps with low parasitic capacitance. Sofics clamps provide standard ESD robustness and do not require a resistance in the signal path.

B. Beyond standard voltage levels

Our IP was used for sensor interfaces, battery connections and more. We have delivered solutions for high voltage tolerance (3.3V and 5V) and also protected interfaces based on thin oxide transistors (0.8V and lower) thanks to a flexible but deterministic solution set.

C. Battery powered applications

Customers have integrated Sofics ESD in IoT systems. The leakage of our ESD cells is 100x lower compared to conventional approach. Huge improvements can be made in stand-by, sleep, operational modes and during power-cycles. Sofics has solutions available for interfaces and rail clamps.

D. Harsh environments

Automotive applications typically require higher ESD robustness levels. Sofics ESD technology can be easily scaled to reach higher HBM and CDM protection levels. In some cases the on-chip ESD cells are adapted to sustain contact discharge 8kV IEC 61000-4-2.

IC products from our customers

Our customers have created amazing products on FinFET processes. Examples include high-speed interfaces for datacenter chips (wired and optical), Artificial Intelligence (AI) processors, automotive ethernet and automotive entertainment chips but also for low-power Internet of Things devices.