Senior Analog Designer

Lab technician

PDK engineer

UPCOMING EVENTS
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ITF Photonics

San Diego [March 5]

OFC

San Diego [March 5-9]

PMF Workshop

Leuven [March 7-8]
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Sofics has proven IP on 10+ foundries. For some foundries, Sofics is part of the eco-system

Foundries

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TSMC | DCA - IP Alliance
SAMSUNG | Safe IP Partner
INTEL | IP Alliance
GLOBAL FOUNDRIES | Design Enablement Network
UMC | IP Alliance
Great partnerships to increase the benefits for IC designers

Our Partners

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Andes Technology Corporation
Etopus
GUC
IMEC IC Link
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Mixel
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Sharing insights from our research and projects
Latest Blog Posts
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April 14, 2023

Protecting die-2-die interfaces…

At Sofics we get a lot of questions about the required ESD robustness for the die-2-die (D2D) interfaces between chiplets.
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February 10, 2023

ESD basic: Silicon Control Rectifier (SCR)

SCR intro: Silicon-controlled rectifiers (SCRs) are interesting devices that can be used for on-chip ESD protection, if (and only if).
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January 26, 2023

ggNMOS (grounded-gated NMOS)

ggNMOS intro: For decades, a traditional workhorse device for ESD protection for standard applications in CMOS technology has been the.
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Contact us to discuss your next IC design
Let’s Work Together
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    Or contact us by email: bd@sofics.com, phone: +32 9 21 68 333 (Belgium)