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People developing Data Center chips benefit from custom ESD protection solutions. The main bottleneck is the speed at which data can be transferred. To enable high-speed communication designers use thin-oxide transistors and low voltage signal protocols at the SerDes/PCIe interface.

In the past the short distance (between racks) connections relied on electrical communication while the long distance, between data centers, uses optical communication. These days even for the short distance optical communication is used.

Custom ESD requirements

There are several reasons why IC designers developing AI products require custom ESD solutions

High-speed communication between compute and memory require I/Os and ESD protection with low parasitic capacitance

Data center AI chips used for training new models are manufactured on the most advanced FinFET processes for the highest performance. The core transistors on these processes are very sensitive to ESD stress. Effective ESD protection clamps are required

AI chips are among the biggest ICs ever made. That is important to consider because the transient current during CDM stress is higher for bigger dies and packages.

To conserve energy, Edge AI applications should use low leakage ESD protection concepts

Sofics IP for Data Centers

Key focus areas

A. High-Speed interfaces

Sofics IP is used for many high-speed data interfaces (wired and optical). These interfaces need ESD clamps with low parasitic capacitance. Sofics clamps provide standard ESD robustness and do not require a resistance in the signal path.

B. die-2-die interface protection

In recent silicon photonics applications the optical and electrical functions are combined in a single module using 3D stacking of different dies. The connections between the different dies (die-2-die interfaces) require custom ESD solutions.

C. Low voltage signaling

High frequency interfaces are built with thin oxide transistors. They also frequently run at a low signal voltage, below the standard I/O voltage range. Sofics has delivered ESD protection solutions for the most sensitive transistors on CMOS and FinFET processes and operating at a voltage of 1V or lower.

D. High CDM stress levels

Data center chips are typically very large dies. However, the larger the package, the higher the peak current is during CDM stress events. Moreover, these chips rely on advanced FinFET processes that are most sensitive during those fast transient events. It is imperative to use fast, local ESD clamps to limit the voltage drop during fast transients.

IC products from our customers

Our customers have created unique products. Several companies are developing modules for rack-to-rack communication based on optical interfaces.

Other customers focus on the compute aspects with high performance Artificial Intelligence functions. These huge chips rely on Sofics solutions for CDM protection.

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