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People developing Data Center chips benefit from custom ESD protection solutions. The main bottleneck is the speed at which data can be transferred. To enable high-speed communication designers use thin-oxide transistors and low voltage signal protocols at the SerDes/PCIe interface.

In the past the short distance (between racks) connections relied on electrical communication while the long distance, between data centers, uses optical communication. These days even for the short distance optical communication is used.

Custom ESD requirements

There are several reasons why IC designers developing AI products require custom ESD solutions

High-speed communication between compute and memory require I/Os and ESD protection with low parasitic capacitance

Data center AI chips used for training new models are manufactured on the most advanced FinFET processes for the highest performance. The core transistors on these processes are very sensitive to ESD stress. Effective ESD protection clamps are required

AI chips are among the biggest ICs ever made. That is important to consider because the transient current during CDM stress is higher for bigger dies and packages.

To conserve energy, Edge AI applications should use low leakage ESD protection concepts

Sofics IP for Data Centers

Key focus areas

A. High-Speed interfaces

Sofics IP is used for many high-speed data interfaces (wired and optical). These interfaces need ESD clamps with low parasitic capacitance. Sofics clamps provide standard ESD robustness and do not require a resistance in the signal path.

ESD with low capacitance

B. die-2-die interface protection

In recent silicon photonics applications the optical and electrical functions are combined in a single module using 3D stacking of different dies. The connections between the different dies (die-2-die interfaces) require custom ESD solutions.

Die-2-die interfaces

C. Low voltage signaling

High frequency interfaces are built with thin oxide transistors. They also frequently run at a low signal voltage, below the standard I/O voltage range. Sofics has delivered ESD protection solutions for the most sensitive transistors on CMOS and FinFET processes and operating at a voltage of 1V or lower.

Thin oxide protection

D. High CDM stress levels

Data center chips are typically very large dies. However, the larger the package, the higher the peak current is during CDM stress events. Moreover, these chips rely on advanced FinFET processes that are most sensitive during those fast transient events. It is imperative to use fast, local ESD clamps to limit the voltage drop during fast transients.

Clamps with high ESD robustness

Process technology covered

Advanced CMOS (40nm to 22nm)

FinFET technology

BiCMOS technology

Foundries covered

TSMC

GlobalFoundries

IC products from our customers

Our customers have created unique products. Several companies are developing modules for rack-to-rack communication based on optical interfaces.

Other customers focus on the compute aspects with high performance Artificial Intelligence functions. These huge chips rely on Sofics solutions for CDM protection.

"Confidence in our chosen partners is critical to us – Sofics offered us flexibility with customization, a proven silicon ESD portfolio and fast time to market. Within just a few weeks we went from first contact to contract to solution delivery."

Phil Horsfield

VP Silicon at Graphcore
“Thanks to our close collaboration with TSMC in the IP alliance, Sofics was able to transfer its proprietary ESD portfolio to the most advanced 5nm process technology”

Koen Verhaege

CEO of Sofics
“We have invested in bringing our proprietary ESD portfolio to the most advanced FinFET technology”

Koen Verhaege

CEO of Sofics
“This defines one of our key roles in the IP eco-system: reducing time-to-market and optimizing customer profit by mitigating the risk, expenses and delays of ESD re-design”

Koen Verhaege

CEO of Sofics
“Fabless companies will always benefit from a shorter timeline and a lower cost combined with the confidence of a working solution.”

Koen Verhaege

CEO of Sofics
“With Sofics’ technology, Lantiq’s 130nm and 65nm HP products are more economic for a wide range of chip-hostile environments”

Christoph von Schierstädt

Lantiq Communications Manager
“Sofics’ ESD solutions together with Lantiq’s best-in-class Telecom products thus create a triple-win solution for Sofics, Lantiq and its customers”

Christoph von Schierstädt

Lantiq Communications Manager
“We’re used to working in different processes, so we can quickly analyze how an existing ESD design will perform in another process node such as their proprietary SiGe BiCMOS.”

Koen Verhaege

CEO of Sofics
“Sofics has been a strong supporter of the drive to improve the reliability of electronics, and has achieved several breakthroughs in ESD protection”

Noboru Shiono

Senior Manager of RCJ
“With the addition of  TakeCharge on-chip ESD protection design solutions to the UMC IP Alliance Program, UMC customers will have easy access to superior ESD design solutions from an industry wide  recognized leader in its field”

Ken Liou

director of the IP and Design Support Division at UMC
“Our alliance with UMC means that customers will achieve shorter design cycles for proven specialty solutions optimized with advanced ESD protection. Together, Sarnoff and UMC can better meet the specialized needs of our customers by bringing cost efficient, higher-quality solutions to market much faster.”

Koen Verhaege

CEO at Sofics
“Sofics combines IP in an advanced design flow with calculation and integration tools, and customized services. They complement the diverse Design Services offered by our portfolio of DCA partners,”

Tom Quan

Deputy Director at the Design Methodology and Service Marketing at TSMC
"Sofics is excited and honored to cooperate with TSMC. Our mission is to empower customers with advanced solutions and tools so they can independently perform successful ESD design, getting it right the first time, every time, regardless of the complexity of the process, application or innovation."

Koen verhaege

CEO at Sofics
“Fujitsu selected TakeCharge to help continue our tradition of providing customers with highly reliable high-performance products and services based on powerful technologies,”

Shoji Ichino

general manager, Technology Development Division, Electronic Devices Business Unit of Fujitsu Limited.
“System manufacturers are increasingly asking IC suppliers for CDM-protected devices. Based on our previous success with TakeCharge CDM protection solution will help us meet that challenge and further solidify Toshiba's competitive position.”

Naoyuki Shigyo

chief specialist in the Analog CAD Engineering Department of Toshiba’s Semiconductor Company
Toshiba has been using technology based on TakeCharge to protect its CMOS ICs from Human Body Model (HBM) and Machine Model (MM) ESD since 2000. The approach has been applied to high-volume 0.18μm, 0.13μm, and 90nm products.

Naoyuki Shigyo

chief specialist in the Analog CAD Engineering Department of Toshiba’s Semiconductor Company
“We are collaborating with industry-leading IP providers to give our customers access to high-quality IPs. We are pleased to welcome Sofics to our IFS Accelerator IP Alliance”

Suk Lee, VP of Design Ecosystem Development at IFS

Director
“We are collaborating with industry-leading IP providers to give our customers access to high-quality IPs. We look forward to continued collaboration with Sofics to enable our customers to enjoy a proven selection of ESD protection IPs.”

Suk Lee, VP of Design Ecosystem Development at IFS

Director
“We look forward to working with Intel Foundry to support mutual customers with our proprietary ESD technology.”

Koen Verhaege, CEO of Sofics

Director

Further reading

Blog article “Optimized Local I/O ESD Protection in FinFET Technology for 2.5D and 3D hybrid integration“

Blog article “Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology“

Blog article “Optical communication also requires ESD protection“

ESD protection for FinFET processes

Press announcement about Sofics IP availability on TSMC 16nm, 12nm and 7nm FinFET nodes

Press announcemet about Sofics IP available on TSMC 5nm FinFET

Press release about our cooperation with Graphcore (UK)

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