Improve your IC performance with PowerQubic technology
For many applications IC designers cannot use the foundry provided GPIO’s or foundry ESD protection clamps.
For instance, excessive leakage prevents low-power circuits. High parasitic capacitance limits interface bandwidth.
Below are examples where Sofics IP can improve IC or interface performance.
On-chip ESD/EOS/Latch up/EMC protection for high voltage and BCD processes
A. Low leakage requirement
Whether self-powered, or for single-use or rechargeable batteries, low power consumption is a key aspect for implantable electronics. Of course, the power consumption only needs to be monitored at 37°C – as opposed to automotive applications where specifications up to 150°C are very common. From an ESD perspective, the leakage is required to remain well below 1nA.
25pA at room temperature for 5V pin in TSMC BCD 0.18um GENII
20pA at room temperature, 100nA at 150°C for 7V operation in TSMC BCD 0.18um GENII
1nA at room temperature, 900nA at 65V for avoiding thermal damage in TSMC BCD 0.18um GENII
B. Under voltage tolerant/miswiring
Many ICs have sub-systems that can be powered down to reduce power consumption: only a small part of the system is awake all the time. All the other circuits are turned off unless required. Traditional ESD protection can ruin the efforts when signals applied on the I/O circuits power-up a functional block not required at that time. Sofics has many protection schemes that allow a voltage at the I/O pad with the Vdd powered off, without causing a leakage path.
power down compatible ESD protection at -40V, TSMC 180nm BCD GENI