Improve your IC performance with TakeCharge technology
For many applications IC designers cannot use the foundry provided GPIO’s or foundry ESD protection clamps.
For instance, excessive leakage prevents low-power circuits. High parasitic capacitance limits interface bandwidth.
Below are examples where Sofics IP can improve IC or interface performance.
On-chip ESD/EOS/Latch up protection for advanced and low voltage processes
A. Non-standard signal voltages
Several IoT systems include sensor interfaces with distinctive signal conditions (5V or even 20V), beyond the typical general purpose I/O provided by the foundry. A lot of our customers request 5V tolerant ESD for e.g. battery connection (4.5V-5V battery), legacy interface communication, or USB. Sofics engineers built 5V tolerant ESD protection clamps in CMOS from 180nm to 16nm using the standard process. In 28nm, we even went up to 12V, on special request from our customer, having only 1.8V transistors at our disposal.
12V tolerant ESD protection in 28nm LV CMOS – delivered
5.5V and 6V tolerant ESD protection in 55nm LV CMOS – first time right
5V tolerant ESD protection in 180nm LV CMOS – mass production.
B. Low leakage requirement
A lot of the IoT applications run on a battery or use energy harvesting. The reduction of leakage in functional circuits is paramount. Foundries provide special low-power process options to reduce both standby and dynamic power. It would not be acceptable to nullify all that work through the use of leaky ESD clamps.
0.18um BCD: 25pA @ 5V, Room Temperature – implemented in a medical application
55nm: 30pA @ 5V, Room Temperature, 70pA @5V, 125°C – proven in IoT volume production
16nm FinFET: 40pA @ 0.9V Room Temperature, 10nA @ 0.9V, 125°C – ready for market introduction
C. Sub-system power down
Many ICs have sub-systems that can be powered down. Often this is implemented to reduce power: only a small part of the system is awake all the time. All the other circuits are turned off unless required. Traditional ESD protection can ruin the efforts when signals applied on the I/O circuits power-up a functional block not required at that time. Sofics engineers have developed many protection schemes that allow a voltage at the I/O pad with the Vdd powered off, without causing a leakage path.
8 power domains and higher with different operation modes – delivered
D. Multi-purpose IO’s
Some I/O’s have a build-in flexibility to change functionality. This is often the case for programmable devices. The ESD protection needs to be flexible as well. It needs to work at different supply voltages, often integrates over-voltage tolerant requirements; protecting multiple and complex I/O structures. Sofics’ track record includes protection of FPGA’s (Microsemi, Altera) or programmable IoT I/O’s.
programmable pin used as general purpose IO or antenna pin – Protected
E. Enabling core transistors in the I/O for high speed/frequency
Key to high speed or high frequency designs, is the utilization of the fastest transistors available in the process: the low voltage (core) NMOS. This is frequently not allowed by the foundries design rule manual in I/O’s, because their high sensitivity for ESD. Sofics’ TakeCharge portfolio offers solutions for these high speed transistors to be placed in the I/O’s, to enable the fastest PHY’s.
1.0V transistors in IO ring for 28nm – achieved
F. Low capacitance for high speed/frequency
Today many communication channels work at (very) high frequencies. The main figure-of-merit for ESD protection for these cases is a low parasitic capacitance for a given ESD level. Both the junction as well as the metal capacitance needs to be taken into account. Sofics has many customers working in this domain (e.g. in Photonics) and has consistently lowered capacitance for their interfaces.
7.5fF in 90nm SiGe for 200V HBM – Photonics
13.4fF in 28nm CMOS for 200V HBM – Photonics
50fF in 90nm SiGe for 500V HBM – 5V over-voltage tolerant pin
57.6fF in 28nm CMOS for 1kV HBM – Communication IC
98.62 fF in 90nm CMOS for 2kV HBM – Communication IC