Increase your IC robustness with TakeCharge technology
Sofics technology helps fabless designers to increase the robustness of their integrated circuits.
Below are examples how this was achieved.
On-chip ESD/EOS/Latch up protection for advanced and low voltage processes
A. Scalable on-chip HBM (MM) levels
Some applications need higher ESD robustness levels. For instance: 4kV HBM for IoT, or 8kV for HDMI (or DisplayPort) pins are fairly common specifications. Sofics’ solutions can be scaled to any level – from 1kV or 2kV HBM to 8kV and higher – for one pin, or for full chip. And the same goes for MM – should your application require this spec. Note that in some cases we can scale down as well: to 100V HBM in combination with extremely low capacitance (smaller then 10fF) requirements for instance.
8kV HBM requirement for HMDI – successful.
B. Higher on-chip CDM levels
CDM is the most important ESD reliability specification, but also the most difficult to reach and to predict. Sofics’ dedicated design approach, based on VF-TLP (very fast Transmission Line Pulser), helps to make CDM more predictable and to achieve the desired levels. A lot of parameters influence the end results (such as die size, package size, air humidity, test (method) used etc.).
500V CDM is routinely met with Sofics’ solutions.
C. Meeting system level ESD on-chip
A lot of the innovative systems target low-cost and mobile applications – and also this relates to ESD. To reduce the system size and the bill of materials, system designers remove board level ESD protection from the mini-Printed Circuit Boards (PCB). 20 years ago, such Transient Voltage Suppressor (TVS) devices were added to protect ICs against ESD stress during the actual use of products. Without such TVS protection and due to the shorter PCB traces ICs are now more severely stressed under ESD test events like IEC 61000-4-2. Moreover, the probability of ESD stress is much higher in mobile systems as they are operated in harsh environments.
IEC 61000-4-2 protection for IoT applications.
D. EOS protection
For a timing controller IC, designed in a 0.13um CMOS process, an EOS specification was given: passing 17V on the IEC-61000-4-5 test. Sofics engineers developed a calculation algorithm to make the result predictable and optimized the I/O’s to reach 17V compliance. The resulting product passed the required level first time right, and the customer was able to scale subsequent ICs to any new, desired level.
Scalable IEC-61000-4-5 performance in volume production ICs.
SEL (Single Event Latchup) can cause upset in systems in high radiation fields. Aerospace is one typical application, but other examples may include particle detectors/accelerators or even nuclear applications. Sofics gained a strong reputation in the field, with customers in a wide variety of applications, developing ICs in often advanced CMOS technologies.
Sofics’ solutions meeting specifications up to 120 LET.