Reduce IC cost – PowerQubic

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Reduce your IC cost with PowerQubic technology

Fabless companies that integrate Sofics IP in their IC designs have been able to reduce their costs spanning across reduced design cost, reduced mask and manufacturing costs, lower risks and reduced time-to-market. Below are examples how this was achieved.


On-chip ESD/EOS/Latch up/EMC protection for high voltage and BCD processes

A. Design cost reduction

Designing ESD protection can be very costly: frequently many test structures are required, analysis needs to be done, IP positions need to be checked and respected…. Sofics has a wide range of solutions, for a wide range of applications, silicon proven in a wide range of processes. As an IP provider, we can distribute the ESD design cost over many different customers, lowering the cost for everyone.

Solutions proven in 20+ high voltage/BCD processes.

B. Mask cost reduction

Nowhere the task of selecting the optimal, minimal mask set is more challenging than in BCD processes. Often a large variety of options are available. So far, Sofics always succeeded in creating protection using only the masks available for the functional elements of the IC.

Minimum mask set – regularly achieved

C. Manufacturing cost reduction

In one example, a customer had a working product (an LCD driver), but the ESD protection consumed too much area. Sofics optimized the diode size and layout, reduced the I/O bus scheme and area, designed a new Sofics power clamp, and worked out a calculation sheet to determine optimum power clamp placement. This resulted in a 25% I/O size reduction, and an overall die area reduction of more than 12%, significantly cutting the product’s manufacturing cost. Since the Sofics engagement the customer has been able to make consistently smaller I/O’s and power cells, and has reduced the power clamp repetition rate. These enhancements lead to smaller and hence cheaper product dies. The customer has been rewarded with significantly increased competitiveness and a bigger market share.

$10’s to $100’s per wafer cost reduction – in volume production.

D. Speed up time-to-market

Designing ESD protection can be very time consuming: often at least one silicon run is required, often setting back the IC design for a couple of months. Sofics has a wide range of solutions, for a wide range of applications, silicon proven in a wide range of processes, readily available at your fingertips.

Less than 1 month from first contact to contract delivery of first time right solutions – achieved

E. Risk reduction

Typical ICs designed in high voltage or BCD processes end up in harsh to very harsh environments, such as automotive or industrial applications. Robustness requirements reach far beyond merely ESD specifications. Sofics’ approach with PowerQubic is to anticipate as much as possible the interaction of specifications and protection structures against the myriad of electrical hazards – optimizing for overall robustness..

IC/module/system failure risk reduction due to broad spec/hazard focus.

F. Proven portability

BCD processes are all very different, and portability for one process or process generation to the next can trigger the need for a series of test chips in order to investigate process properties during various disturbances. Sofics has developed work-arounds enabling ESD protection for high voltage pins, often without the need for a test chip. In one example, a product IC was protected up to 4kV HBM and 200V MM in an untested 0.18um BCD process. The holding voltage of the protection was designed and delivered at 28V, well above the required 24V.

Blind porting of a 24V clamp to a new BCD process – successful