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Protecting die-2-die interfaces…

by Bart Keppens
Posted on April 14, 2023
in 2.5D and 3D hybrid integration, ESD protection, FinFET, SerDES

At Sofics we get a lot of questions about the required ESD robustness for the die-2-die (D2D) interfaces between chiplets in a package. People wonder how to select the right ESD standard and what robustness level they need to design for. Sofics has supported several chiplet projects for AI, data center communication applications recently.

by kverhaege
Posted on February 10, 2023
in DTSCR, dual diode, ESD protection, ESD protection approaches, FinFET, Local clamp, SCR, Silicon controlled rectifier, SOI

SCR intro: Silicon-controlled rectifiers (SCRs) are interesting devices that can be used for on-chip ESD protection, if (and only if) they are properly designed and biased. SCRs are used for high-speed/RF or low-capacitance, small area/high-performance ESD solutions in all CMOS technologies, including SOI and FinFET (down to 3nm today). SCR operation: Figure 1 introduces theContinue[...]

by kverhaege
Posted on January 26, 2023
in ESD protection, ESD protection approaches, ggnmos, Local clamp, power clamp

ggNMOS intro: For decades, a traditional workhorse device for ESD protection for standard applications in CMOS technology has been the grounded-gate NMOS device (ggNMOS). Nevertheless, we have been explaining the operation of this device countless times, including as recently as 3 weeks ago. So, it is time for a short blog article. The schematic ofContinue[...]

Sofics' CEO outlook for 2023... 2023 will be a year of opportunity to invest in our readiness to grow and flourish in 2024. Whatever your semiconductor business, your key assets: team, skills, technology, processes, and reputation, should not go to waste.

by Bart Keppens
Posted on August 9, 2022
in CMOS, DTSCR, ESD devices, ESD protection, FinFET, Local clamp, Low capacitance ESD, Optical communication, Paper, SCR, SerDES, SiGe BiCMOS, Silicon controlled rectifier, SOI, TakeCharge, Wired communication

Sofics' 2021 IEDS publication. Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.

Automotive electronics ESD protection_cutour

by Bart Keppens
Posted on July 1, 2022
in Automotive, BCD, BCD technology, ESD protection, High ESD or IEC 61000-4-2 robustness, High voltage tolerance, IEC 61000-4-2, Latch-up immunity, LIN transceiver, PhyStar, PowerQubic, System Basic Chips

Due to the semiconductor shortage in 2021 everyone realized that cars these days integrate a lot of electronics. The average number of computer chips per car has increased a lot in the last decade. It is clear that the new applications require high-speed interconnects that are not possible with the initial, low-speed interface types. But[...]

Imagers and image processing ESD protection_cutour

by Bart Keppens
Posted on June 1, 2022
in 2.5D and 3D hybrid integration, 3D integration, CMOS, ESD design window, ESD protection, High voltage tolerance, Imagers, Local clamp, Low capacitance ESD, Silicon controlled rectifier, Wired communication

Today, you can find CMOS image sensors almost everywhere in consumer, automotive, health and security applications. There has been a lot of innovation to enable demanding requirements. The article provides a summary about the 3 main aspects that IC designers need to consider when selecting the ESD protection clamps for their image sensor projects.

by Bart Keppens
Posted on May 27, 2022
in Automotive, CMOS, Display, EOS, ESD design window, ESD protection, ESD protection approaches, ESD testing, High Voltage, High voltage tolerance, IEC 61000-4-5, Local clamp, Over voltage tolerant, overvoltage tolerant, PowerQubic, TakeCharge

EOS, or Electrical Overstress, is any electrical stress that exceeds any of the specified absolute maximum ratings (AMR) of a product. It is important to discuss because many products are damaged this way. This article includes case studies and 3 approaches to handle those requests.

by Bart Keppens
Posted on May 18, 2022
in Automotive, CMOS, dual diode, ESD protection, ESD protection approaches, Ethernet, FinFET, High ESD or IEC 61000-4-2 robustness, High speed interfaces, Local clamp, Low capacitance ESD, SerDES, TakeCharge, Wired communication

In the past most Electronic Control Units (ECU) used CAN and LIN interfaces to connect to sensors, actuators and each other. However, the newest applications need (much) faster communication options. Gigabit automotive ethernet is pushed by many in the industry as the perfect solution. With its local ESD clamp approach, Sofics provides the best solution[...]

by tomako85
Posted on April 6, 2022
in ESD devices, ESD protection, ESD protection approaches, GPIO, IO, SOFICS, TSMC

Fabless semiconductor companies usually use third-party IP blocks when developing ICs. An important IP is on-chip ESD protection. Caution must be exercised in choosing the right ESD IP to avoid patent infringement and inefficient ESD clamps. Thomas Ako made a presentation about the IP selection process on the 2021 IP-SOC event in Grenoble in December 2021.

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Protecting die-2-die interfaces…

ESD basic: Silicon Control Rectifier (SCR)

ggNMOS (grounded-gated NMOS)

Let’s talk about 2023

Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology

New opportunities for automotive LIN interfaces

Selecting optimized ESD protection for CMOS image sensors

3 approaches to handle EOS ‘requirements’

Optimized on-chip ESD protection to enable high-speed Ethernet in cars.

Selecting custom ESD IP for your next IC

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Latest News

ESD protection for Internet-of-Things (IoT)

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