High signal voltage tolerance

ESD clamps with high voltage tolerance

Sofics technology has been applied for many different applications. Some applications need I/O that can tolerate a higher voltage.

Examples in different processes

Examples for different process nodes are shown below. This is just a subset of cells proven on silicon and in mass production.

Cells can be ported to other processes. The actual numbers (ESD robustness, leakage, capacitance, area) may vary slightly, also depending on the circuit to be protected, process, voltage level.

Mature CMOS (0.5um to 180nm)

Process	Pad	ESD robustness	Leakage
TSMC 180nm	5V rail	> 8 kV HBM	< 5 nA
TSMC 180nm	5V I/O	> 8 kV HBM	< 5 nA
TSMC 180nm	7V I/O	> 2 kV HBM	< 50 nA
TowerSemi 350nm	4.5V rail	> 8 kV HBM	< 100 pA

Mainstream CMOS (130nm to 65nm)

Process	pad	ESD robustness	Leakage
TSMC 130nm	5V rail	> 3 kV HBM	< 1 nA
TSMC 130nm	5V I/O	> 3 kV HBM	< 1 nA
TSMC 130nm	7V I/O	> 4 kV HBM	< 1 nA
TSMC 65nm	5V I/O OVT	> 4 kV HBM	< 1 nA
TSMC 65nm	5V I/O	> 4 kV HBM	< 100 nA

Advanced CMOS (40nm to 22nm)

Process	Pad	ESD robustness	Leakage
TSMC 40nm	5V rail	> 2 kV HBM	< 10 nA
TSMC 40nm	5V I/O	> 2 kV HBM	< 10 nA
TSMC 28nm	3.9V I/O	> 2 kV HBM	< 50 pA
TSMC 28nm	5.5V I/O	> 2 kV HBM	< 400 pA
TSMC 28nm	6.5V I/O	> 2 kV HBM	< 400 pA
TSMC 28nm	12V I/O	> 2 kV HBM	< 40 nA
UMC 28nm	8.6V I/O	> 500V HBM	< 1 uA

FinFET technology

Process	Pad	ESD robustness	Leakage
TSMC 16nm	5V rail	> 1 kV HBM	< 30 nA
TSMC 16nm	5V I/O	> 1 kV HBM	< 30 nA
TSMC 12nm	3.3V rail	> 3 kV HBM	< 60 nA
TSMC 12nm	5V I/O	> 4 kV HBM	< 3 uA
TSMC 7nm	3.3V rail	> 2 kV HBM	< 1.5 uA
TSMC 5nm	1.8V rail	> 1 kV HBM	< 500 pA

SOI technology

Process	Pad	ESD robustness	Leakage
GF 22FDX	3.3V rail	> 5 kV HBM	< 10 pA
GF 22FDX	3.3V I/O	> 2 kV HBM	< 500 pA
GF 22FDX	5V rail	> 4 kV HBM	< 10 nA

BiCMOS technology

Process	Pad	ESD robustness	Parasitic capacitance
TSMC 130nm	1.2V I/O	> 4 kV HBM	< 100 fF
TSMC 130nm	1.2V I/O OVT	> 2 kV HBM	< 50 fF
UMC 130nm	1.2V I/O	> 2 kV HBM	< 150 fF
TSMC 90nm	3.3V I/O	> 2kV HBM	< 100 fF
TSMC 65nm	1.8V I/O	> 4 kV HBM	< 100 fF
TSMC 65nm	1.0V I/O	> 3 kV HBM	< 70 fF
GF 65nm	1.2V I/O	> 2 kV HBM	< 50 fF
GF 65nm	3.3V I/O	> 2 kV HBM	< 50 fF

Other ways to search our IP

Check the benefits for each application type

Browse Sofics IP based on Process technology

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Customer quotes

“We needed to protect a 15V interface on a 0.18um high-voltage LDMOS chip that we will produce for our customer. The IC contains both the 15V interface and digital logic circuits. Sofics' PowerQubic technology offered a great solution and Sofics delivered it in just two weeks."

Hugh Durdan

eSilicon COO

“Thanks to our close collaboration with TSMC in the IP alliance, Sofics was able to transfer its proprietary ESD portfolio to the most advanced 5nm process technology”

Koen Verhaege

CEO of Sofics

“We have invested in bringing our proprietary ESD portfolio to the most advanced FinFET technology”

Koen Verhaege

CEO of Sofics

“We are delighted that our patent application for our unique clipping technology was granted. This PhyStar circuit will reduce cost and risk for many IC companies working on NFC designs”

Koen Verhaege

CEO of Sofics

“This defines one of our key roles in the IP eco-system: reducing time-to-market and optimizing customer profit by mitigating the risk, expenses and delays of ESD re-design”

Koen Verhaege

CEO of Sofics

“Fabless companies will always benefit from a shorter timeline and a lower cost combined with the confidence of a working solution.”

Koen Verhaege

CEO of Sofics

"Sofics and ICsense came up with a solution for us that works at high voltages and provides good ESD protection”

Pete Hughes

Vice President, Mobile, NVIDIA

“Integration of overvoltage tolerance with ESD protection delivers both technical and cost benefits”

Koen Verhaege

CEO of Sofics

“We wanted true 3.3V signalling on our new baseband chip without the extra cost of 2.5V/3.3V masks. By integrating ESD protection with high-voltage capability, the Sofics/ICsense team gave us the ability to safely handle off-chip interfaces up to 3.6 volts with 1.8-volt internal transistors”

Peter Hughes

Icera Vice President of Silicon Engineering and Operations

“The design worked right the first time.”

Peter Hughes

Icera Vice President of Silicon Engineering and Operations

“Our TakeCharge® technology contributed full ESD protection up to 4kV HBM and 300V MM while reducing the silicon footprint of the I/O pads”

Koen Verhaege

CEO at Sofics

“ICsense used our high-voltage-in-low-voltage expertise to achieve tolerances of -0.3V to 3.9V. This allows chips to communicate reliably under a wide range of start-up and power scenarios, with robust ESD protection”

Bram De Muer

ICsense CEO

“PowerQubic provides cost-effective, cutting-edge IC and system-level protection for high-voltage circuit designs”

Koen Verhaege

CEO at Sofics

“We’re gratified that after extensive testing TSMC has selected our technology to help customers protect their high-voltage circuits.”

Koen Verhaege

CEO at Sofics

“Sofics has been a strong supporter of the drive to improve the reliability of electronics, and has achieved several breakthroughs in ESD protection”

Noboru Shiono

Senior Manager of RCJ

“With the addition of TakeCharge on-chip ESD protection design solutions to the UMC IP Alliance Program, UMC customers will have easy access to superior ESD design solutions from an industry wide recognized leader in its field”

Ken Liou

director of the IP and Design Support Division at UMC

“Our alliance with UMC means that customers will achieve shorter design cycles for proven specialty solutions optimized with advanced ESD protection. Together, Sarnoff and UMC can better meet the specialized needs of our customers by bringing cost efficient, higher-quality solutions to market much faster.”

Koen Verhaege

CEO at Sofics

“Sofics combines IP in an advanced design flow with calculation and integration tools, and customized services. They complement the diverse Design Services offered by our portfolio of DCA partners,”

Tom Quan

Deputy Director at the Design Methodology and Service Marketing at TSMC

"Sofics is excited and honored to cooperate with TSMC. Our mission is to empower customers with advanced solutions and tools so they can independently perform successful ESD design, getting it right the first time, every time, regardless of the complexity of the process, application or innovation."

Koen verhaege

CEO at Sofics

"By utilizing TakeCharge in designing the I/O area of our HV-CMOS devices, we will be able to offer new ICs with improved capabilities even faster than before"

Yoshiyuki Miyayama

General Manager of the IC Design Technology Department in Epson’s Semiconductor Operations Division.

“Ricoh is committed to delivering high-performance, cost-effective products to our customers. We are reinforcing that commitment by adding TakeCharge technology to our extensive IC design resources.”

Akira Nakamura

General Manager Ricoh

“We are collaborating with industry-leading IP providers to give our customers access to high-quality IPs. We are pleased to welcome Sofics to our IFS Accelerator IP Alliance”

Suk Lee, VP of Design Ecosystem Development at IFS

Director

“We are collaborating with industry-leading IP providers to give our customers access to high-quality IPs. We look forward to continued collaboration with Sofics to enable our customers to enjoy a proven selection of ESD protection IPs.”

Suk Lee, VP of Design Ecosystem Development at IFS

Director

“We look forward to working with Intel Foundry to support mutual customers with our proprietary ESD technology.”

Koen Verhaege, CEO of Sofics

Director

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