Low parasitic capacitance

ESD clamps with low parasitic capacitance

Sofics technology has been applied for many different applications. Specifically for high-speed interfaces or high-bandwidth wireless applications the parasitic capacitance of the ESD cells need to be as low as possible.

Sofics solutions typically have 30% to 50% lower capacitance compared to the foundry solutions with the same ESD robustness.

Examples in different processes

Examples for different process nodes are shown below. This is just a subset of cells proven on silicon and in mass production.

All cells can be ported to other processes. The actual numbers (ESD robustness, leakage, capacitance, area) may vary slightly, also depending on the circuit to be protected, process, voltage level.

Mature CMOS (0.5um to 180nm)

Process	Pad	ESD robustness	Parasitic capacitance
TSMC 180nm	1.8V I/O	>5 kV HBM	<300 fF
TSMC 180nm	5V I/O	> 8 kV HBM	300 fF
TSMC 180nm	7V I/O	> 2 kV HBM	< 200 fF
TowerSemi 350nm	4.5V I/O	> 8 kV HBM	< 550 fF

Mainstream CMOS (130nm to 65nm)

Process	Pad	ESD robustness	Parasitic capacitance
TSMC 130nm	1.2V I/O	> 4 kV HBM	< 100 fF
TSMC 130nm	1.2V I/O OVT	> 2 kV HBM	< 50 fF
UMC 130nm	1.2V I/O	> 2 kV HBM	< 150 fF
TSMC 90nm	3.3V I/O	> 2kV HBM	< 100 fF
TSMC 65nm	1.8V I/O	> 4 kV HBM	< 100 fF
TSMC 65nm	1.0V I/O	> 3 kV HBM	< 70 fF
GF 65nm	1.2V I/O	> 2 kV HBM	< 50 fF
GF 65nm	3.3V I/O	> 2 kV HBM	< 50 fF

Advanced CMOS (40nm to 22nm)

Process	Pad	ESD robustness	Parasitic capacitance
TSMC 40nm	3.3V I/O	> 5 kV HBM	< 180 fF
TSMC 40nm	1.2V I/O	> 4 kV HBM	< 180 fF
TSMC 40nm	1.8V I/O	> 2 kV HBM	< 70 fF
TSMC 28nm	0.85V I/O	> 2 kV HBM	< 100 fF
TSMC 28nm	1.0V I/O	> 100 V HBM	<11 fF
TSMC 28nm	1V I/O	> 200 V HBM	< 15 fF
TSMC 28nm	1.5V I/O	> 1 kV HBM	< 60 fF
UMC 28nm	1.0V I/O	> 1.5 kV HBM	65 fF
TSMC 22nm	0.8V I/O	> 8 kV HBM	< 500 fF

FinFET technology

Process	Pad	ESD robustness	Parasitic capacitance
TSMC 16nm	1.0V I/O	> 1 kV HBM	< 80 fF
TSMC 16nm	1.0V I/O	> 2 kV HBM	100 fF
TSMC 12nm	1.8V I/O	> 3 kV HBM	300 fF
TSMC 7nm	0.9V I/O	> 400 V HBM	50 fF
TSMC 7nm	0.9V I/O	> 150 V HBM	15 fF
TSMC 7nm	0.9V I/O	> 80 V HBM	10 fF
TSMC 6nm	0.9V I/O	> 100V HBM	13 fF
TSMC 5nm	0.9V I/O	> 1 kV HBM	90 fF
Samsung 4nm	1.2V I/O	> 2 kV HBM	230 fF

SOI technology

Process	Pad	ESD robustness	Parasitic capacitance
TSMC 130nm	1.2V I/O	> 4 kV HBM	< 100 fF
TSMC 130nm	1.2V I/O OVT	> 2 kV HBM	< 50 fF
UMC 130nm	1.2V I/O	> 2 kV HBM	< 150 fF
TSMC 90nm	3.3V I/O	> 2kV HBM	< 100 fF
TSMC 65nm	1.8V I/O	> 4 kV HBM	< 100 fF
TSMC 65nm	1.0V I/O	> 3 kV HBM	< 70 fF
GF 65nm	1.2V I/O	> 2 kV HBM	< 50 fF
GF 65nm	3.3V I/O	> 2 kV HBM	< 50 fF

BiCMOS technology

Process	Pad	ESD robustness	Parasitic capacitance
GF 9HP	2.5V I/O	> 2 kV HBM	< 50 fF
GF 9HP	2.5V I/O	> 200 V HBM	< 10 fF
GF 9HP	2.5V I/O	500 V HBM	< 10 fF

Other ways to search our IP

Check the benefits for each application type

Browse Sofics IP based on Process technology

Learn about the benefits of Sofics technology

Customer quotes

The implementation of TakeCharge will allow us to effectively manage ESD protection while continuing to quickly and cost-effectively deliver our next-generation, low-power programmable products to market.

Dr. Esmat Hamdy

senior vice president of technology and operations at Actel Corporation

We chose TakeCharge® technology for our FPGA product families as part of Altera’s commitment to deliver high-performance, cost-effective programmable products to our customers. TakeCharge® has allowed us to effectively manage both ESD protection and IO area.

Bradley Howe

vice president of IC Design at Altera

“It is clear that IC designers that integrate Mixel’s MIPI IP can benefit from close collaboration between design teams at Mixel, Sofics, and Hardent”

Ashraf Takla

Mixel CEO and President

“To ensure good signal integrity, the MIPI PHY interfaces need to be paired with analog I/Os with low parasitic capacitance.”

Koen Verhaege

CEO of Sofics

“Thanks to our close collaboration with TSMC in the IP alliance, Sofics was able to transfer its proprietary ESD portfolio to the most advanced 5nm process technology”

Koen Verhaege

CEO of Sofics

“We have invested in bringing our proprietary ESD portfolio to the most advanced FinFET technology”

Koen Verhaege

CEO of Sofics

“This defines one of our key roles in the IP eco-system: reducing time-to-market and optimizing customer profit by mitigating the risk, expenses and delays of ESD re-design”

Koen Verhaege

CEO of Sofics

“Fabless companies will always benefit from a shorter timeline and a lower cost combined with the confidence of a working solution.”

Koen Verhaege

CEO of Sofics

“With Sofics’ technology, Lantiq’s 130nm and 65nm HP products are more economic for a wide range of chip-hostile environments”

Christoph von Schierstädt

Lantiq Communications Manager

“Sofics’ ESD solutions together with Lantiq’s best-in-class Telecom products thus create a triple-win solution for Sofics, Lantiq and its customers”

Christoph von Schierstädt

Lantiq Communications Manager

“Sofics delivered a customized ESD solution in less than a week”

William McFadden

VP Operations at DecaWave

“TakeCharge was also far more cost-effective than other approaches to ESD protection”

William McFadden

VP Operations at DecaWave

“Sofics has been a strong supporter of the drive to improve the reliability of electronics, and has achieved several breakthroughs in ESD protection”

Noboru Shiono

Senior Manager of RCJ

“With the addition of TakeCharge on-chip ESD protection design solutions to the UMC IP Alliance Program, UMC customers will have easy access to superior ESD design solutions from an industry wide recognized leader in its field”

Ken Liou

director of the IP and Design Support Division at UMC

“Our alliance with UMC means that customers will achieve shorter design cycles for proven specialty solutions optimized with advanced ESD protection. Together, Sarnoff and UMC can better meet the specialized needs of our customers by bringing cost efficient, higher-quality solutions to market much faster.”

Koen Verhaege

CEO at Sofics

“Sofics combines IP in an advanced design flow with calculation and integration tools, and customized services. They complement the diverse Design Services offered by our portfolio of DCA partners,”

Tom Quan

Deputy Director at the Design Methodology and Service Marketing at TSMC

"Sofics is excited and honored to cooperate with TSMC. Our mission is to empower customers with advanced solutions and tools so they can independently perform successful ESD design, getting it right the first time, every time, regardless of the complexity of the process, application or innovation."

Koen verhaege

CEO at Sofics

“Using Sofics' ESD solutions we significantly lower our technical and business risks and expenses."

Kenji Numata

Senior Manager, System LSI Design Department of Toshiba’s Semiconductor Company

"This makes TakeCharge our standard choice solution for ESD protection, and we offer its unique benefits to our customers."

Kenji Numata

Senior Manager, System LSI Design Department of Toshiba’s Semiconductor Company

"Reuse of TakeCharge IP in Toshiba’s 180nm to 65nm ASIC products has consistently resulted in robust Charged Device Model (CDM), Human Body Model (HBM) and Machine Model (MM) performance.”

Kenji Numata

Senior Manager, System LSI Design Department of Toshiba’s Semiconductor Company

“We are dedicated to Toshiba’s business success in 32nm and beyond, and in the arena of COT and foundry services. The expanded licensing agreement will enable us to further strengthen the technical collaboration with Toshiba’s ESD team in the years to come.”

Koen Verhaege

CEO at Sofics

“The TakeCharge Design Kit enabled RedMere to quickly and economically increase our IC ESD performance to a new HDMI industry standard of 8kV HBM without compromising the stringent operation requirements of a 3.4Gbps data channel. They truly demonstrated the ease-of-use and scalability of their solutions”.

Peter Smyth

CEO of RedMere Technology

“RedMere Technology’s selection of TakeCharge to aid in a successful first to-market introduction of their HDMI application proves the trust semiconductor companies have placed in the effectiveness of i-our ESD solutions"

Koen Verhaege

CEO at Sofics

“TakeCharge enables design engineers to access the most advanced on-chip, extreme low-capacity and area efficient ESD solutions."

Koen Verhaege

CEO at Sofics

“Fujitsu selected TakeCharge to help continue our tradition of providing customers with highly reliable high-performance products and services based on powerful technologies,”

Shoji Ichino

general manager, Technology Development Division, Electronic Devices Business Unit of Fujitsu Limited.

“TakeCharge technology can reduce the capacitance of the input and output (I/O) pins of HV-CMOS IC’s. Therefore, its application can reduce the power required to drive the data bus”

Fumihisa Nakamura

Category Director, Display Driver and PDP, System LSI Division of Matsushita Semiconductor Company.

“We had faced many ESD problems which could not be solved easily two decades ago, especially on thin gate oxide process. Now, few ESD problems appear in our IC development, thanks to ESD protection technology that has been licensed from Sofics.”

Top-10 Semiconductor company

Director

“We are collaborating with industry-leading IP providers to give our customers access to high-quality IPs. We are pleased to welcome Sofics to our IFS Accelerator IP Alliance”

Suk Lee, VP of Design Ecosystem Development at IFS

Director

“We are collaborating with industry-leading IP providers to give our customers access to high-quality IPs. We look forward to continued collaboration with Sofics to enable our customers to enjoy a proven selection of ESD protection IPs.”

Suk Lee, VP of Design Ecosystem Development at IFS

Director

“We look forward to working with Intel Foundry to support mutual customers with our proprietary ESD technology.”

Koen Verhaege, CEO of Sofics

Director