Radiation hard and cold-spare

Radiation hard and cold-spare ESD solutions

Sofics has supported several companies in the past on radiation tolerant applications and other harsh environments. We worked both on prevention of Single Event Latch-up and on prevention of degradation due to Total dose irradiation.

Examples

Sofics ESD technology and knowledge used for rad-hard applications

We have provided our Analog IOs and ESD clamps to CERN for use in their experiments. They have sourced technology from us in 130nm, 65nm and 28nm.

We have delivered ESD clamps to a large US based FPGA maker that sources its solutions to aerospace applications. They ran tests (@ Berkeley) on our 65nm solutions and did not see failures up to 120 LET

We have supported a few companies in their ASIC design for use in satellites.

We have supported companies developing radiation hard products or libraries

Mature CMOS (0.5um to 180nm)

Process	Pad	ESD robustness	Leakage
TSMC 180nm	5V rail	> 8 kV HBM	< 5 nA
TSMC 180nm	5V I/O	> 8 kV HBM	< 5 nA
TSMC 180nm	7V I/O	> 2 kV HBM	< 50 nA
TowerSemi 350nm	4.5V rail	> 8 kV HBM	< 100 pA

Mainstream CMOS (130nm to 65nm)

Process	pad	ESD robustness	Leakage
TSMC 130nm	5V rail	> 3 kV HBM	< 1 nA
TSMC 130nm	5V I/O	> 3 kV HBM	< 1 nA
TSMC 130nm	7V I/O	> 4 kV HBM	< 1 nA
TSMC 65nm	5V I/O OVT	> 4 kV HBM	< 1 nA
TSMC 65nm	5V I/O	> 4 kV HBM	< 100 nA

Advanced CMOS (40nm to 22nm)

Process	Pad	ESD robustness	Leakage
TSMC 40nm	5V rail	> 2 kV HBM	< 10 nA
TSMC 40nm	5V I/O	> 2 kV HBM	< 10 nA
TSMC 28nm	3.9V I/O	> 2 kV HBM	< 50 pA
TSMC 28nm	5.5V I/O	> 2 kV HBM	< 400 pA
TSMC 28nm	6.5V I/O	> 2 kV HBM	< 400 pA
TSMC 28nm	12V I/O	> 2 kV HBM	< 40 nA
UMC 28nm	8.6V I/O	> 500V HBM	< 1 uA

FinFET technology

Process	Pad	ESD robustness	Leakage
TSMC 16nm	5V rail	> 1 kV HBM	< 30 nA
TSMC 16nm	5V I/O	> 1 kV HBM	< 30 nA
TSMC 12nm	3.3V rail	> 3 kV HBM	< 60 nA
TSMC 12nm	5V I/O	> 4 kV HBM	< 3 uA
TSMC 7nm	3.3V rail	> 2 kV HBM	< 1.5 uA
TSMC 5nm	1.8V rail	> 1 kV HBM	< 500 pA

SOI technology

Process	Pad	ESD robustness	Leakage
GF 22FDX	3.3V rail	> 5 kV HBM	< 10 pA
GF 22FDX	3.3V I/O	> 2 kV HBM	< 500 pA
GF 22FDX	5V rail	> 4 kV HBM	< 10 nA

BiCMOS technology

Process	Pad	ESD robustness	Parasitic capacitance
TSMC 130nm	1.2V I/O	> 4 kV HBM	< 100 fF
TSMC 130nm	1.2V I/O OVT	> 2 kV HBM	< 50 fF
UMC 130nm	1.2V I/O	> 2 kV HBM	< 150 fF
TSMC 90nm	3.3V I/O	> 2kV HBM	< 100 fF
TSMC 65nm	1.8V I/O	> 4 kV HBM	< 100 fF
TSMC 65nm	1.0V I/O	> 3 kV HBM	< 70 fF
GF 65nm	1.2V I/O	> 2 kV HBM	< 50 fF
GF 65nm	3.3V I/O	> 2 kV HBM	< 50 fF

Other ways to search our IP

Check the benefits for each application type

Browse Sofics IP based on Process technology

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Customer quotes

“You can’t afford failures in outer space. We chose Sofics because it gives us access to the expertise behind the most advanced technology in ESD diagnostics and solutions, and because they routinely work in multiple processes. This reduces risk and saves time and money.”

Daniel González

leader of the microelectronics group of Arquimea

“This defines one of our key roles in the IP eco-system: reducing time-to-market and optimizing customer profit by mitigating the risk, expenses and delays of ESD re-design”

Koen Verhaege

CEO of Sofics

“Fabless companies will always benefit from a shorter timeline and a lower cost combined with the confidence of a working solution.”

Koen Verhaege

CEO of Sofics

“We’re used to working in different processes, so we can quickly analyze how an existing ESD design will perform in another process node such as their proprietary SiGe BiCMOS.”

Koen Verhaege

CEO of Sofics

“Sofics has been a strong supporter of the drive to improve the reliability of electronics, and has achieved several breakthroughs in ESD protection”

Noboru Shiono

Senior Manager of RCJ

“With the addition of TakeCharge on-chip ESD protection design solutions to the UMC IP Alliance Program, UMC customers will have easy access to superior ESD design solutions from an industry wide recognized leader in its field”

Ken Liou

director of the IP and Design Support Division at UMC

“Our alliance with UMC means that customers will achieve shorter design cycles for proven specialty solutions optimized with advanced ESD protection. Together, Sarnoff and UMC can better meet the specialized needs of our customers by bringing cost efficient, higher-quality solutions to market much faster.”

Koen Verhaege

CEO at Sofics

“Sofics combines IP in an advanced design flow with calculation and integration tools, and customized services. They complement the diverse Design Services offered by our portfolio of DCA partners,”

Tom Quan

Deputy Director at the Design Methodology and Service Marketing at TSMC

"Sofics is excited and honored to cooperate with TSMC. Our mission is to empower customers with advanced solutions and tools so they can independently perform successful ESD design, getting it right the first time, every time, regardless of the complexity of the process, application or innovation."

Koen verhaege

CEO at Sofics

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