• High performance analog I/O's

  • Higher signal voltage ratings
  • Low power
  • High robustness
  • High speed/RF

Non-standard signal voltages
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Several interfaces have distinctive signal conditions (5V or even 20V), for instance for battery connection (4.5V-5V battery), legacy interface communication, or USB.
Sofics engineers built 5V and beyond tolerant ESD protection clamps in CMOS from 180nm to 12nm using the standard process.

  • 5.5V and 6V tolerant ESD protection in 55nm LV CMOS – first time right
  • up to 12V tolerant ESD protection in 28nm LV CMOS – delivered

Low power requirement
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The reduction of leakage in functional circuits is paramount. Sofics' has a specialized set of solution with extremely low standby power.

  • 0.18um BCD: 25pA @ 5V, Room Temperature – implemented in a medical application
  • 55nm: 30pA @ 5V, Room Temperature, 70pA @5V, 125°C – proven in IoT volume production
  • 16nm FinFET: 40pA @ 0.9V Room Temperature, 10nA @ 0.9V, 125°C – ready for market introduction

High Robustness
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Sometimes 1 or 2 kV HBM is not enough: some PHY's or IC need higher ESD protection ratings. Some even require system-level ESD protection on-chip!
Any ESD performance is possbile in all process nodes - ask us!

  • 4kV in TMSC 16nm FinFETs - First time right
  • 6kV in UMC 65nm - First time right
  • 8kV in TowerJazz 350nm - First time right

Low capacitance for high speed/frequency
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To get the most out of the process technology, the I/O's must support the highest frequencies. To achieve this, Sofics' proposes a twofold method:
  • Allow thin gate devices in the I/O
  • Reduce parasitic capacitance

  • 13.4fF in 28nm CMOS for 200V HBM – Photonics
  • 50fF in 90nm SiGe for 500V HBM – 5V over-voltage tolerant pin
  • 57.6fF in 28nm CMOS for 1kV HBM – Communication IC
  • 98.62fF in 90nm CMOS for 2kV HBM – Communication IC