Non-standard signal voltages
Several IoT systems include sensor interfaces with distinctive signal conditions (5V or even 20V), beyond the typical general purpose I/O provided by the foundry. A lot of our customers request 5V tolerant ESD for e.g. battery connection (4.5V-5V battery), legacy interface communication, or USB. Sofics engineers built 5V tolerant ESD protection clamps in CMOS from 180nm to 16nm using the standard process. In 28nm, we even went up to 12V, on special request from our customer, having only 1.8V transistors at our disposal.
- 12V tolerant ESD protection in 28nm LV CMOS – delivered
- 5.5V and 6V tolerant ESD protection in 55nm LV CMOS – first time right
- 5V tolerant ESD protection in 180nm LV CMOS – mass production
Low leakage requirement
A lot of the IoT applications run on a battery or use energy harvesting. The reduction of leakage in functional circuits is paramount. Foundries provide special low-power process options to reduce both standby and dynamic power. It would not be acceptable to nullify all that work through the use of leaky ESD clamps.
- 0.18um BCD: 25pA @ 5V, Room Temperature – implemented in a medical application
- 55nm: 30pA @ 5V, Room Temperature, 70pA @5V, 125°C – proven in IoT volume production
- 16nm FinFET: 40pA @ 0.9V Room Temperature, 10nA @ 0.9V, 125°C – ready for market introduction
- 0.18um BCD: 25pA @ 5V, Room Temperature – implemented in a medical application
- 55nm: 30pA @ 5V, Room Temperature, 70pA @5V, 125°C – proven in IoT volume production
- 16nm FinFET: 40pA @ 0.9V Room Temperature, 10nA @ 0.9V, 125°C – ready for market introduction
Sub-system power down
Many ICs have sub-systems that can be powered down. Often this is implemented to reduce power: only a small part of the system is awake all the time. All the other circuits are turned off unless required. Traditional ESD protection can ruin the efforts when signals applied on the I/O circuits power-up a functional block not required at that time. Sofics engineers have developed many protection schemes that allow a voltage at the I/O pad with the Vdd powered off, without causing a leakage path.
8 power domains and higher with different operation modes - delivered