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Programmable clipping circuit

Last year, about 40% of new smartphones included Near Field Communication (NFC). According to analysts there are now 1 billion NFC enabled phones. Clearly, the use of NFC is ramping up because it can simplify aspects as diverse as communication, secure payments, user authentication, and retail loyalty programs for instance. Adding NFC functionality to an integrated circuit involves connecting the wireless interface pins to an antenna/coil. The voltage on those pads strongly depend on the distance between and alignment of transmit/read devices and the power of the transmitting device. The voltage can easily run above 10V, beyond the maximum tolerated voltage of the sensitive circuits. There are basically 2 ways to cope with this excess voltage.

  • Use high voltage transistors
    Fortunately, many NFC applications require on-chip non-volatile memory (NVM) circuits for foundries provide high voltage transistors/process flavors. Several of Sofics’ customers have used those thick gate oxide NVM transistors for the first stage of the antenna circuit. However, high voltage transistors are easily damaged during electrostatic discharge (ESD) stress… A parallel on-chip ESD protection circuit (with 10V tolerance) is the easiest solution.

    Sofics ESD clamps for the protection of NFC antenna pads – proven in several technology nodes

  • Limit the voltage
    It is possible to reduce the excess voltage with a so-called clipping or limiting circuit. The simple approach is to use a set of diodes but due to the large amount of current the diode perimeter is rather large. This leads to high leakage current during non-clipped operation. Sofics has designed a novel clipping circuit to solve those issues. The clipping circuit was used to protect the NFC antenna pads in an ultra-low power Bluetooth chip with ‘Touch-to-pair’ functionality, produced in TSMC 55nm CMOS.

    Sofics clipping circuit in mass production – used broadly in home automation and IoT applications

IO with high EOS robustness

Some interfaces require a higher tolerance against EOS. Due to a lack of a better standards, companies tend to use IEC 61000-4-5 as reference to define the EOS tolerance. Sofics has been involved in the design of EOS tolerant IO's up to 17V in a typical 130nm process.

IEC 61000-4-5 protection upto 17V in 0.13um CMOS - successful

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