Higher on-chip CDM levels
CDM is the most important ESD reliability specification, but also the most difficult to reach and to predict. Sofics’ dedicated design approach, based on VF-TLP (very fast Transmission Line Pulser), helps to make CDM more predictable and to achieve the desired levels. A lot of parameters influence the end results (such as die size, package size, air humidity, test (method) used etc.).
500V CDM is routinely met with Sofics’ solutions
For a timing controller IC, designed in a 0.13um CMOS process, an EOS specification was given: passing 17V on the IEC-61000-4-5 test. Sofics engineers developed a calculation algorithm to make the result predictable and optimized the I/O’s to reach 17V compliance. The resulting product passed the required level first time right, and the customer was able to scale subsequent ICs to any new, desired level.
Scalable IEC-61000-4-5 performance in volume production ICs