- Reduce your IC cost
- Reduce design, mask and wafer cost
- Reduce time-to-market
- Reduce risk
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Protection for low voltage
and advanced processes
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Case Study
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Low design cost
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Pre-developed solutions
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Customized and optimized per application
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Low mask cost
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Compatible with standard process flow
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No additional masks
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Skipping ESD mask to save ~40$/wafer
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Low wafer cost
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Small silicon area
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Reduce silicon cost by 1 to 10%
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Time-to-market
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First time right
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Pre-developed
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Easy access to support engineers
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Risk reduction
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Proven solutions
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Silicon proven
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Product proven
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Clean IP portfolio
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Protection for high voltage
and BCD processes
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-
Case Study
-
Low design cost
-
Pre-developed solutions
-
Customized and optimized per application
-
-
Low mask cost
-
Compatible with standard process flow
-
No additional masks
-
-
Low wafer cost
-
Small silicon area
-
-
-
Time-to-market
-
First time right
-
Pre-developed
-
Easy access to support engineers
-
Risk reduction
-
Proven solutions
-
Silicon proven
-
Product proven in 10 processes
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Clean IP portfolio
-
-
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Low design cost
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Allow your team to focus on
core circuit development
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Customized and optimized per applications
-
Low wafer cost
-
Smaller silicon footprint
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Time-to-market
-
First time right
-
Easy access to support engineers
-
-
Risk reduction
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Leveraging design-for-robustness expertise
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