Many, if not all, ICs require a circuit to put all logic in a known state
when the IC is powered up: a power-on-reset circuit - sometimes combined with
brown-out detection, a circuit which detects a dip in the supply voltage and subsequently resets the IC.
Unfortunately, the reset can also be triggered at unwanted times, during an ESD event for instance.
Sofics PoR circuit is designed to minimize the risk of unwanted resets.
- Avoid unwanted resets with Sofics' PoR
Sofics' PoR: more than 100 years of combined ESD experience put at work to improve the way your IC resets - or does not reset.
In combination with Sofics ESD clamps, hard and soft failures during disturbances are minimized, and reset happens when required, but only when required.
The Sofics PoR, including brown out detection, is silicon proven in TSMC 0.25um BCD, but easily portable to any node.
- 100 years of experience at work for you