• ESD protection for FinFET technology




ESD protection in FinFET technology is challenging




  • Circuits fail easily

  • The maximum allowed voltage on core circuits continues to drop.

  • Traditional concepts fail

  • In FinFET processes traditional ESD clamps are not effective anymore

  • Free libraries introduce limitations

  • Most foundries provide IO libraries for free. However, for several applications the general purpose IOs introduce all kinds of limitations.



Chip designers need new solutions




  • Ensure robust ICs

  • Protect against electrical stress like ESD, EOS. Prevent latch-up and EMC issues.

  • Enhance performance

  • Remove limits introduced by traditional concepts: designers need low-leakage ESD clamps, can tolerate higher voltage and do not introduce a lot of parasitic capacitance.

  • Reduce IC cost

  • Reduce the cost of design with proven technology. Reduce production cost with small ESD concepts. Reduce risk and time-to-market.



Sofics has the perfect solution for FinFET technologies

Sofics has verified its TakeCharge ESD protection clamps on several FinFET technologies.




  • Proven technology

  • Sofics ESD technology has been included in 3000+ mass-produced IC designs, corresponding to millions of wafers. The solutions have successfully been transferred to FinFET technology including 16nm, 12nm and 7nm nodes.

  • Broad solution spectrum

  • Sofics has ESD solutions for the different power domains and for every type of interface. The clamps are used in Analog IO's and can be used to protect digital IO's. The technology can be easily customized to fit various requirements.

  • Beyond standard specifications

  • Sofics creates ESD clamps with ultra-low parasitic capacitance for high speed interfaces like 112Gbps. Clamps can be scaled to high ESD robustness like 8kV HBM. Sofics ESD protection clamps have very low stand-by leakage and if needed can tolerate a higher voltage.



Sofics can support your next FinFET design

  • 16nm

  • Silicon verified on dedicated test chip in 2017

  • Product verification: 4 licensees have integrated our low-cap ESD clamps to protect SerDes circuits (28Gbps - 56GBps)

  • Volume production

  • Download our 16nm datasheet

  • Contact us to get a measurement report.

  • 12nm

  • Silicon verified on dedicated test chip

  • Silicon verification - similar very good results to 16nm.

  • Product verification: 2 licensees have integrated our IP for the protection of SerDes circuits (56Gbps - 112Gbps)


  • 7nm

  • Dedicated ESD test chip taped in March 2019

  • Silicon in our lab; analysis completed by end of August 2019; first results are excellent

  • Product verification: 3 licensees. Pre-silicon cell delivery, including low-cap ESD in March and July 2019. Integration into SerDes IP blocks for one licensee later in 2019

  • Project negotiation on-going with 3 more customers. Discussions on-going with again 4 other companies, all requesting low-cap ESD for SerDes circuits.


  • N5

  • Dedicated test chip taped in summer 2019

  • Silicon verification: samples expected before end of 2019

  • Pre-silicon design solutions available