• ESD protection for FinFET technology

ESD protection in FinFET technology is challenging



  • FinFET devices are sensitive to ESD stress

  • Traditional, conventional ESD devices are less effective

  • General purpose IO libraries introduce limitations

Sofics has the perfect solution for FinFET technologies

Sofics has verified its TakeCharge ESD protection clamps on several FinFET technologies.



Contact us to discuss ESD protection for your FinFET product.




  • Proven technology

  • Sofics ESD technology has been included in 4500+ mass-produced IC designs, corresponding to millions of wafers. These solutions have now been transferred to FinFET technology including 16nm, 12nm, 7nm and 5nm nodes.

  • Broad solution spectrum

  • Sofics has ESD solutions for the different power domains and for every type of interface. The clamps are used in Analog IO's and can be used to protect digital IO's. The technology can be easily customized to fit various requirements.

  • Beyond standard specifications

  • Sofics creates ESD clamps with ultra-low parasitic capacitance for high speed interfaces like 112Gbps. Clamps can be scaled to high ESD robustness like 8kV HBM. Sofics ESD protection clamps have very low stand-by leakage and if needed can tolerate a higher voltage beyond the GPIO limits.



Sofics can support your next FinFET design

  • 16nm

  • Silicon verified on ESD test chip in 2017
  • Integrated in products from several customers - volume production
  • Low-cap ESD protection for SerDes circuits (28 Gbps - 56 Gbps)
  • Analog I/O capability for 2.5V, 3.3V and 5V


  • 12nm

  • Silicon verified on ESD test chip in 2019
  • Integrated in products from 2 customers
  • Low-cap ESD protection for SerDes circuits (56 Gbps - 112 Gbps)
  • Analog I/O capability for 2.5V, 3.3V and 5V

  • 7nm

  • Silicon verified on ESD test chip in 2019
  • Integration on-going with 4 customers
  • Low-cap ESD protection for SerDes circuits (56 Gbps - 112 Gbps)
  • Analog I/O capability for 2.5V, 3.3V and 5V


  • N5

  • Silicon verified on ESD test chip in 2019
  • Integrated on customer tape out
  • Low-cap ESD protection for SerDes circuits (56 Gbps - 112 Gbps)
  • Analog I/O capability for 1.8V, 2.5V and 3.3V