Development and characterization of on-chip ESD protection IC for high-tech applications
At first, we provide an intensive theoretical training in on-chip ESD protection in all important aspects such as strategy, layout and measurements. This in-house training will take up to a week.
Shortly thereafter, the trainee will be included in the engineering team and assigned to the ongoing research and development projects within our company. Assisted by experienced ESD engineers he gets to know in a very "hands-on" way all aspects of the design and development of advanced ESD solutions for the most diverse processes and applications, ranging from High Voltage technologies for automotive ICs to 5nm FinFET for the SOC (System on Chip) of tomorrow.
The specific task for the trainee will therefore consist of analyzing and evaluating new patented circuits and devices designed to guarantee "system-safe" IC design for a specific application (depending on active projects during the internship). During the internship, the trainee will be able to rely not only on the necessary simulation software, but also on measurement results on real silicon samples. For this we have specialized equipment available (lab in Aalter) which will enable the trainee to perform or replicate all tests to which modern high-tech ICs are exposed.