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On-chip ESD protection for
low voltage/advanced processes
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Proven in more than 50 different processes
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More than 4500 commercially released ICs
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Foundry independent
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Low design cost
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Pre-developed solutions
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Customized and optimized per application
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Low mask cost
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Compatible with standard process flow
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No additional masks
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Skipping ESD mask to save ~40$/wafer
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Low wafer cost
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Small silicon area
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Reduces silicon cost by 1 to 10%
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Time-to-market
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First time right
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Pre-developed
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Easy access to support engineers
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Risk reduction
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Proven solutions
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Silicon proven
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Product proven
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Clean IP portfolio
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Any ESD model
Any level
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Human Body Model (HBM)
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Machine Model (MM)
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Charge Device Model (CDM)
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System level ESD on-chip
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Hand Metal Model (HMM)
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Any disturbance
Any level
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Static latch up: JEDEC78
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Transient latch up
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Electrical Overstress (EOS): IEC 61000-4-5 ...
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High frequency applications
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Optimize junction and metal capacitance
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Optimize for Common Mode Rejection Ratio
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Low power applications
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Minimize static leakage
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Low noise applications
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Complex ground/power bus architectures
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Compatible with any start up sequence
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Overvoltage designs
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No diode to supply allowed
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Hot swap
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Allow plug in during power up
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Undervoltage designs
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Miswiring conditions
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Under- and overvoltage designs
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eg. antenna pins
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