• On-chip ESD protection for
    low voltage/advanced processes

  • Proven in more than 50 different processes

  • More than 4500 commercially released ICs

  • Foundry independent


  • Check our list of qualified technologies

  • Low design cost

  • Pre-developed solutions

  • Customized and optimized per application


  • Low mask cost

  • Compatible with standard process flow

  • No additional masks

  • Skipping ESD mask to save ~40$/wafer

  • Low wafer cost

  • Small silicon area

  • Reduces silicon cost by 1 to 10%


  • Time-to-market

  • First time right

  • Pre-developed

  • Easy access to support engineers

  • Risk reduction

  • Proven solutions

  • Silicon proven

  • Product proven

  • Clean IP portfolio



  • Any ESD model
    Any level

  • Human Body Model (HBM)

  • Machine Model (MM)

  • Charge Device Model (CDM)

  • System level ESD on-chip

  • Hand Metal Model (HMM)

  • Any disturbance
    Any level

  • Static latch up: JEDEC78

  • Transient latch up

  • Electrical Overstress (EOS): IEC 61000-4-5 ...


  • High frequency applications

  • Optimize junction and metal capacitance

  • Optimize for Common Mode Rejection Ratio

  • Low power applications

  • Minimize static leakage

  • Low noise applications

  • Complex ground/power bus architectures

  • Compatible with any start up sequence

  • Overvoltage designs

  • No diode to supply allowed


  • Hot swap

  • Allow plug in during power up

  • Undervoltage designs

  • Miswiring conditions

  • Under- and overvoltage designs

  • eg. antenna pins


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