Protecting chip interfaces in FinFET nodes against Electrostatic Discharge (ESD) needs dedicated attention. ESD remains an important reliability issue for semiconductor companies. ESD events can occur during several stages in the development, assembly and actual use of the ICs.
Sofics has verified its ESD protection clamps on 9 different FinFET process nodes at TSMC and Samsung Foundry. Integrating our solutions can enhance your competitive advantage.
There are 3 reasons why ESD solutions on FinFET technology is challenging
Basic building blocks like FinFET transistors are very sensitive to ESD stress.
Traditional ESD approaches are no longer effective.
The design complexity has increased a lot.
Moreover, the foundry provided General Purpose I/O libraries introduce contraints. For instance the voltage range of the I/O libraries prevents communication with legacy chips running at 3V or higher. The parasitic capacitance of the integrated ESD protection clamps is too high for interfaces running at speeds beyond 10 Gbps. The leakage current of traditional ESD clamps prevents low-power applications.
There are 3 reasons why ESD solutions on FinFET technology is challenging
Basic building blocks like FinFET transistors are very sensitive to ESD stress.
Traditional ESD approaches are no longer effective.
The design complexity has increased a lot.
Moreover, the foundry provided General Purpose I/O libraries introduce contraints. For instance the voltage range of the I/O libraries prevents communication with legacy chips running at 3V or higher. The parasitic capacitance of the integrated ESD protection clamps is too high for interfaces running at speeds beyond 10 Gbps. The leakage current of traditional ESD clamps prevents low-power applications.
TSMC 16nm
TSMC 12nm
TSMC 7nm
TSMC 6nm
TSMC 5nm
TSMC 3nm test chip
Samsung Foundry 14nm
Samsung Foundry 8nm
Samsung Foundry 5nm
Samsung Foundry 4nm
Sofics IP on FinFET is used in high bandwidth communication interfaces for wired and optical networks including 28Gbps, 56Gbps and 112Gbps SerDes. These interfaces need ESD clamps with low parasitic capacitance. Sofics clamps provide standard ESD robustness and do not require a resistance in the signal path.
Our IP was used for sensor interfaces, battery connections and more. We have delivered solutions for high voltage tolerance (3.3V and 5V) and also protected interfaces based on thin oxide transistors (0.8V and lower) thanks to a flexible but deterministic solution set.
Customers have integrated Sofics ESD in IoT systems. The leakage of our ESD cells is 100x lower compared to conventional approach. Huge improvements can be made in stand-by, sleep, operational modes and during power-cycles. Sofics has solutions available for interfaces and rail clamps.
Automotive applications typically require higher ESD robustness levels. Sofics ESD technology can be easily scaled to reach higher HBM and CDM protection levels. In some cases the on-chip ESD cells are adapted to sustain contact discharge 8kV IEC 61000-4-2.
Our customers have created amazing products on FinFET processes. Examples include high-speed interfaces for datacenter chips (wired and optical), Artificial Intelligence (AI) processors, automotive ethernet and automotive entertainment chips but also for low-power Internet of Things devices.
Blog article “Optimized Local I/O ESD Protection in FinFET Technology for 2.5D and 3D hybrid integration“
Blog article “Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology“
Blog article “Optical communication also requires ESD protection“
ESD protection for FinFET processes
Press announcement about Sofics IP availability on TSMC 16nm, 12nm and 7nm FinFET nodes
Press announcement about Sofics IP available on TSMC 5nm FinFET
Press announcement about the partnership with Intel Foundry
Press release about our cooperation with Graphcore (UK)
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