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Chip designers working on ICs produced at Silterra can use the (free) General Purpose I/O (GPIO) library for the chip interfaces. These GPIOs also include conventional ESD protection devices.

However, for some applications this traditional ESD approach limits the designer. Constraints include high leakage, high parasitic capacitance, large area, fixed ESD robustness and limited signal voltage options.

Sofics IP for Silterra

Key focus areas

A. Wireless interfaces

Sofics IP is used for many high-speed and wireless interfaces. These interfaces need ESD clamps with low parasitic capacitance. Sofics clamps provide standard ESD robustness and do not require a resistance in the signal path.

B. Battery powered applications

For certain application like IoT, edge AI, medical devices, the power consumption must be reduced. The leakage of Sofics’ ESD cells is 100x lower compared to conventional approach. Huge improvements can be made in stand-by, sleep, operational modes and during power-cycles.

C. Enhanced ESD robustness

Some applications require higher ESD robustness, well beyond the typical 2kV HBM. Our ESD clamps can be easily scaled to any ESD/EOS protection level. We have delivered ESD clamps for 4kV, 8kV HBM as well as for 8kV IEC 61000-4-2.

D. High signal voltage tolerance

Applications designed on CMOS processes typically use low signal voltages below 3.3V. However, there are several reasons that designers want to use a higher signal voltage like 5V or even higher. Sofics has developed ESD devices that can handle those requirements.

Process technology covered

Mainstream CMOS (130nm to 65nm)

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