Stay Connected:

Archive

Home - Archive by taxonomy: Latch-Up Immunity

Mr. Shiratori

“… consistently manufacture chips that perform at high voltages with full electrostatic discharge (ESD) and latch-up protection. We have implemented these TakeCharge devices in our various high volume products, such as LCD and OLED driver devices, where they deliver substantial added value for Oki and its customers.”
Read More

Koen Verhaege

“We are dedicated to Toshiba’s business success in 32nm and beyond, and in the arena of COT and foundry services. The expanded licensing agreement will enable us to further strengthen the technical collaboration with Toshiba’s ESD team in the years to come.”
Read More

Kenji Numata

“Reuse of TakeCharge IP in Toshiba’s 180nm to 65nm ASIC products has consistently resulted in robust Charged Device Model (CDM), Human Body Model (HBM) and Machine Model (MM) performance.”
Read More

Koen verhaege

“Sofics is excited and honored to cooperate with TSMC. Our mission is to empower customers with advanced solutions and tools so they can independently perform successful ESD design, getting it right the first time, every time, regardless of the complexity of the process, application or innovation.”
Read More

Tom Quan

“Sofics combines IP in an advanced design flow with calculation and integration tools, and customized services. They complement the diverse Design Services offered by our portfolio of DCA partners,”
Read More

Koen Verhaege

“Our alliance with UMC means that customers will achieve shorter design cycles for proven specialty solutions optimized with advanced ESD protection. Together, Sarnoff and UMC can better meet the specialized needs of our customers by bringing cost efficient, higher-quality solutions to market much faster.”
Read More

Ken Liou

“With the addition of  TakeCharge on-chip ESD protection design solutions to the UMC IP Alliance Program, UMC customers will have easy access to superior ESD design solutions from an industry wide  recognized leader in its field”
Read More