ON-CHIP ESD SOLUTIONS AT YOUR FINGERTIPS

Download more info

NEWS

  • Meet us at
  • Read about Sofics case studies on protecting Silicon Photonics
  • New career opportunity
  • Sofics on-chip ESD clamps also protect your IC

    Various applications

    Consumer electronics, Space, industrial, automotive, computer, networking.

    50+ different processes

    CMOS down to 28nm, BCD, SOI.
    16nm FinFet project starting

    1 IC release per day

    60+ customers: IDM, foundry, fabless, start-ups, design service providers,...

    Company introduction

    Reduce your IC costs

    Generic ESD/EOS solutions provide generic protection.
    With Sofics solutions your IC designs benefit from state-of-the-art protection, plus assurance of maximum performance, at a lower total cost. Here's how we do it.

    Lower design and
    development cost

    • Library of solutions available
    • On-chip ESD clamps delivered as plug-n-play
    • Smaller footprint
    • Standard process: no special ESD masks required

    Reduced time to market

    • No development time required: cells available
    • No time wasted on debugging
    • First time right
    • No re-spins

    Reduced risk

    • Reduced exposure to liabilities such as field failures and patent disputes
    • Silicon and product proven cells

    Applications up to 5V   Applications beyond 5V

    Improve IC performance

    Standard ESD solutions can actually hamper the performance of your IC designs. Sofics ESD technology, however, will let your IC deliver high speed, unimpaired analog performance, robust high-voltage interfaces on nano-CMOS SOCs, and other features you need to create a winning product.

    High speed RF capability

    • Enable use of sensitive core transistors for more speed
    • Reduce S11
    • Improve Q-factor
    • Reduce noise
    • Enable 28 Gbps I/Os in 28nm

    Over voltage designs

    • Fail-safe
    • Hot swap
    • Open drain
    • Over voltage tolerant
    • 13V protection in 28nm

    Analog

    • Common Mode Rejection Ratio (CMRR)
    • IO impedance
    • Q-factor
    • noise sensitivity leakage…

    Contact us to discuss your custom need

    Achieve tough specs for ESD, latch-up, and EOS

    Is your IC design facing incredibly stringent electrical overstress specifications? Sofics will meet the challenge to the boundaries of physics with a cost-effective solution.

    On-chip ESD

    • Component level: HBM, MM, CDM
    • System level: IEC61000-4-2

    Latch-up

    • JEDEC 78
    • Transient latch-up

    EOS/EMC

    • 61000-4-5
    • ISO 7637-2
    • IEC 62132

    Learn about our case histories