ON-CHIP ESD SOLUTIONS AT YOUR FINGERTIPS
- - TSMC OIP event in Santa Clara, CA, USA – September 13
- - EOS/ESD Symposium in Tucson, AZ, USA – September 10-14
- - ECOC conference in Goteburg, Sweden – September 17-21
- - GSA entrepreneurship conference at Imec, Leuven, Belgium – September 27
- - GlobalFoundries Tech. conference in Munich, Germany – October 13
Sofics on-chip ESD clamps also protect your IC
Various applicationsConsumer electronics, Space, industrial, automotive, computer, networking.
50+ different processesCMOS down to 28nm, BCD, SOI.
16nm FinFet project starting
1 IC release per day60+ customers: IDM, foundry, fabless, start-ups, design service providers,...
Reduce your IC costsGeneric ESD/EOS solutions provide generic protection.
With Sofics solutions your IC designs benefit from state-of-the-art protection, plus assurance of maximum performance, at a lower total cost. Here's how we do it.
Lower design and
- Library of solutions available
- On-chip ESD clamps delivered as plug-n-play
- Smaller footprint
- Standard process: no special ESD masks required
Reduced time to market
- No development time required: cells available
- No time wasted on debugging
- First time right
- No re-spins
- Reduced exposure to liabilities such as field failures and patent disputes
- Silicon and product proven cells
Improve IC performanceStandard ESD solutions can actually hamper the performance of your IC designs. Sofics ESD technology, however, will let your IC deliver high speed, unimpaired analog performance, robust high-voltage interfaces on nano-CMOS SOCs, and other features you need to create a winning product.
High speed RF capability
- Enable use of sensitive core transistors for more speed
- Reduce S11
- Improve Q-factor
- Reduce noise
- Enable 28 Gbps I/Os in 28nm
Over voltage designs
- Hot swap
- Open drain
- Over voltage tolerant
- 13V protection in 28nm
- Common Mode Rejection Ratio (CMRR)
- IO impedance
- noise sensitivity leakage…
Achieve tough specs for ESD, latch-up, and EOSIs your IC design facing incredibly stringent electrical overstress specifications? Sofics will meet the challenge to the boundaries of physics with a cost-effective solution.
- Component level: HBM, MM, CDM
- System level: IEC61000-4-2
- JEDEC 78
- Transient latch-up
- ISO 7637-2
- IEC 62132