Frequently chip designers need to include high bandwidth interfaces (wired, wireless or optical). For these applications the conventional ESD approach is not effective anymore and custom ESD protection is required.
Custom ESD requirements
IC designers that integrate high bandwidth interfaces on their chips require custom ESD solutions:
High-bandwidth communication require I/Os and ESD protection with low parasitic capacitance
These interfaces are typically designed on the most advanced CMOS and FinFET processes for the highest performance. The core transistors on these processes are very sensitive to ESD stress. Effective ESD protection clamps are required
High speed interfaces run at a voltage below the typical I/O voltage. Custom I/O and ESD circuits are required.
For LNA inputs the leakage of the ESD protection needs to be as low as possible to improve the Q-factor. Low leakage ESD protection concepts come in handy.
Sofics IP for high-bandwidth interfaces
Key focus areas
A. High-Speed interfaces
Sofics IP is used for many high-frequency interfaces (wired, wireless and optical). These interfaces need ESD clamps with low parasitic capacitance. Sofics low-capacitance ESD clamps provide standard ESD robustness and do not require a resistance in the signal path.
B. die-2-die interface protection
Recently, die-2-die interfaces between chiplets require high-bandwidth interfaces. The dies are combined in 2.5D or 3D stacking. These connections can benefit a lot (smaller area, lower parasitic capacitance, lower leakage) from custom ESD solutions with lower robustness.
C. LNA Q-factor
Wireless LNA (inputs) can benefit from low leakage ESD protection. The leakage of Sofics’ ESD cells is 100x lower compared to conventional approach. Huge improvements can be made in the Q-factor for the LNA pads.
D. Low voltage signaling
High frequency interfaces are built with thin oxide transistors. They also frequently run at a low signal voltage, below the standard I/O voltage range. Sofics has delivered ESD protection solutions for the most sensitive transistors on CMOS and FinFET processes and operating at a voltage of 1V or lower.
E. Enhanced ESD robustness
Some interfaces require higher ESD robustness, well beyond the typical 2kV HBM. Typical examples include USB, DisplayPort and HDMI interfaces Our ESD clamps can be easily scaled to any ESD/EOS protection level. We have delivered ESD clamps for 4kV, 8kV HBM as well as for 8kV IEC 61000-4-2.
IC products from our customers
Sofics IP for high frequency interfaces is used in many IC projects from customers in USA, EU, UK, Japan, Taiwan, …
Examples for wired interfaces include HDMI, DisplayPort, SerDes, LVDS, V-by-one, MIPI, USB, PCIexpress, ….
We have supported 15+ projects on high-speed silicon photonics communication.
Our IP is used in wireless interfaces for Bluetooth, Wifi, GPS, 4G, 5G, …
The implementation of TakeCharge will allow us to effectively manage ESD protection while continuing to quickly and cost-effectively deliver our next-generation, low-power programmable products to market.
Dr. Esmat Hamdy
senior vice president of technology and operations at Actel Corporation
We chose TakeCharge® technology for our FPGA product families as part of Altera’s commitment to deliver high-performance, cost-effective programmable products to our customers. TakeCharge® has allowed us to effectively manage both ESD protection and IO area.
Bradley Howe
vice president of IC Design at Altera
Specialized ESD design solutions within a very short turnaround time. They truly demonstrated first-time-right delivery capabilities.
Michel De Mey
Senior Director of Hearing and Audio Solutions at AMIS
Easy-to-use, easy-to-integrate TakeCharge ESD protection solution so we can focus on bringing our cutting-edge industry standard products to customers quickly and cost effectively.
Michel De Mey
Senior Director of Hearing and Audio Solutions at AMIS
The TakeCharge Solution enables full flexibility in our designs in terms of specifications and area efficiency.
Michel De Mey
Senior Director of Hearing and Audio Solutions at AMIS
“It is clear that IC designers that integrate Mixel’s MIPI IP can benefit from close collaboration between design teams at Mixel, Sofics, and Hardent”
Ashraf Takla
Mixel CEO and President
“To ensure good signal integrity, the MIPI PHY interfaces need to be paired with analog I/Os with low parasitic capacitance.”
Koen Verhaege
CEO of Sofics
“Thanks to our close collaboration with TSMC in the IP alliance, Sofics was able to transfer its proprietary ESD portfolio to the most advanced 5nm process technology”
Koen Verhaege
CEO of Sofics
“We have invested in bringing our proprietary ESD portfolio to the most advanced FinFET technology”
Koen Verhaege
CEO of Sofics
“We are delighted that our patent application for our unique clipping technology was granted. This PhyStar circuit will reduce cost and risk for many IC companies working on NFC designs”
Koen Verhaege
CEO of Sofics
“This defines one of our key roles in the IP eco-system: reducing time-to-market and optimizing customer profit by mitigating the risk, expenses and delays of ESD re-design”
Koen Verhaege
CEO of Sofics
“Fabless companies will always benefit from a shorter timeline and a lower cost combined with the confidence of a working solution.”
Koen Verhaege
CEO of Sofics
“With Sofics’ technology, Lantiq’s 130nm and 65nm HP products are more economic for a wide range of chip-hostile environments”
Christoph von Schierstädt
Lantiq Communications Manager
“Sofics’ ESD solutions together with Lantiq’s best-in-class Telecom products thus create a triple-win solution for Sofics, Lantiq and its customers”
Christoph von Schierstädt
Lantiq Communications Manager
“We’re used to working in different processes, so we can quickly analyze how an existing ESD design will perform in another process node such as their proprietary SiGe BiCMOS.”
Koen Verhaege
CEO of Sofics
"Sofics and ICsense came up with a solution for us that works at high voltages and provides good ESD protection”
Pete Hughes
Vice President, Mobile, NVIDIA
“Integration of overvoltage tolerance with ESD protection delivers both technical and cost benefits”
Koen Verhaege
CEO of Sofics
“Sofics delivered a customized ESD solution in less than a week”
William McFadden
VP Operations at DecaWave
“TakeCharge was also far more cost-effective than other approaches to ESD protection”
William McFadden
VP Operations at DecaWave
“We wanted true 3.3V signalling on our new baseband chip without the extra cost of 2.5V/3.3V masks.
By integrating ESD protection with high-voltage capability, the Sofics/ICsense team gave us the ability to safely handle off-chip interfaces up to 3.6 volts with 1.8-volt internal transistors”
Peter Hughes
Icera Vice President of Silicon Engineering and Operations
“The design worked right the first time.”
Peter Hughes
Icera Vice President of Silicon Engineering and Operations
“Our TakeCharge® technology contributed full ESD protection up to 4kV HBM and 300V MM while reducing the silicon footprint of the I/O pads”
Koen Verhaege
CEO at Sofics
“ICsense used our high-voltage-in-low-voltage expertise to achieve tolerances of -0.3V to 3.9V. This allows chips to communicate reliably under a wide range of start-up and power scenarios, with robust ESD protection”
Bram De Muer
ICsense CEO
“Sofics has been a strong supporter of the drive to improve the reliability of electronics, and has achieved several breakthroughs in ESD protection”
Noboru Shiono
Senior Manager of RCJ
“With the addition of TakeCharge on-chip ESD protection design solutions to the UMC IP Alliance Program, UMC customers will have easy access to superior ESD design solutions from an industry wide recognized leader in its field”
Ken Liou
director of the IP and Design Support Division at UMC
“Our alliance with UMC means that customers will achieve shorter design cycles for proven specialty solutions optimized with advanced ESD protection. Together, Sarnoff and UMC can better meet the specialized needs of our customers by bringing cost efficient, higher-quality solutions to market much faster.”
Koen Verhaege
CEO at Sofics
“Sofics combines IP in an advanced design flow with calculation and integration tools, and customized services. They complement the diverse Design Services offered by our portfolio of DCA partners,”
Tom Quan
Deputy Director at the Design Methodology and Service Marketing at TSMC
"Sofics is excited and honored to cooperate with TSMC. Our mission is to empower customers with advanced solutions and tools so they can independently perform successful ESD design, getting it right the first time, every time, regardless of the complexity of the process, application or innovation."
Koen verhaege
CEO at Sofics
“Using Sofics' ESD solutions we significantly lower our technical and business risks and expenses."
Kenji Numata
Senior Manager, System LSI Design Department of Toshiba’s Semiconductor Company
"This makes TakeCharge our standard choice solution for ESD protection, and we offer its unique benefits to our customers."
Kenji Numata
Senior Manager, System LSI Design Department of Toshiba’s Semiconductor Company
"Reuse of TakeCharge IP in Toshiba’s 180nm to 65nm ASIC products has consistently resulted in robust Charged Device Model (CDM), Human Body Model (HBM) and Machine Model (MM) performance.”
Kenji Numata
Senior Manager, System LSI Design Department of Toshiba’s Semiconductor Company
“We are dedicated to Toshiba’s business success in 32nm and beyond, and in the arena of COT and foundry services. The expanded licensing agreement will enable us to further strengthen the technical collaboration with Toshiba’s ESD team in the years to come.”
Koen Verhaege
CEO at Sofics
“The TakeCharge Design Kit enabled RedMere to quickly and economically increase our IC ESD performance to a new HDMI industry standard of 8kV HBM without compromising the stringent operation requirements of a 3.4Gbps data channel. They truly demonstrated the ease-of-use and scalability of their solutions”.
Peter Smyth
CEO of RedMere Technology
“RedMere Technology’s selection of TakeCharge to aid in a successful first to-market introduction of their HDMI application proves the trust semiconductor companies have placed in the effectiveness of i-our ESD solutions"
Koen Verhaege
CEO at Sofics
“TakeCharge enables design engineers to access the most advanced on-chip, extreme low-capacity and area efficient ESD solutions."
Koen Verhaege
CEO at Sofics
“As a specialty foundry, it is important that we provide our fabless customers with a wide range of robust and efficient high-performance ESD protection solutions for all their logic and mixed-signal applications"
Dani Ashkenazi
General Manager CMOS Product Line at Tower Semiconductor
"Sofics has consistently been a reliable and expert ESD protection IP partner to the semiconductor industry, making them the natural choice as our partner for these demanding applications.”
Dani Ashkenazi
General Manager CMOS Product Line at Tower Semiconductor
“We are pleased that Tower Semiconductor selected our technology to provide a high quality ESD protection platform. TakeCharge ESD protection solutions are developed with scalability in mind, and thus can meet high-performance requirements, even up to 20kV HBM.”
Koen Verhaege
CEO at Sofics
“Fujitsu selected TakeCharge to help continue our tradition of providing customers with highly reliable high-performance products and services based on powerful technologies,”
Shoji Ichino
general manager, Technology Development Division, Electronic Devices Business Unit of Fujitsu Limited.
“System manufacturers are increasingly asking IC suppliers for CDM-protected devices. Based on our previous success with TakeCharge CDM protection solution will help us meet that challenge and further solidify Toshiba's competitive position.”
Naoyuki Shigyo
chief specialist in the Analog CAD Engineering Department of Toshiba’s Semiconductor Company
Toshiba has been using technology based on TakeCharge to protect its CMOS ICs from Human Body Model (HBM) and Machine Model (MM) ESD since 2000. The approach has been applied to high-volume 0.18μm, 0.13μm, and 90nm products.
Naoyuki Shigyo
chief specialist in the Analog CAD Engineering Department of Toshiba’s Semiconductor Company
“TakeCharge technology can reduce the capacitance of the input and output (I/O) pins of HV-CMOS IC’s. Therefore, its application can reduce the power required to drive the data bus”
Fumihisa Nakamura
Category Director, Display Driver and PDP, System LSI Division of Matsushita Semiconductor Company.
“Ricoh is committed to delivering high-performance, cost-effective products to our customers. We are reinforcing that commitment by adding TakeCharge technology to our extensive IC design resources.”
Akira Nakamura
General Manager Ricoh
“TakeCharge technology helps us reduce the die size of our chips for greater economy, while maintaining and ensuring ESD protection in all application areas including high speed”
Shigeo Koguchi
President and CEO of Toshiba’s Semiconductor Company
“We’ve had consistent success in designing more compact, higher-performance ESD protection into our ICs with TakeCharge. We will continue to collaborate with Sarnoff to develop solutions for our future processes such as 45nm and 32nm.”
Naoyuki Shigyo
Chief Specialist, System LSI Design Department of Toshiba’s Semiconductor Company
“We had faced many ESD problems which could not be solved easily two decades ago, especially on thin gate oxide process.
Now, few ESD problems appear in our IC development, thanks to ESD protection technology that has been licensed from Sofics.”
Top-10 Semiconductor company
Director
“We are collaborating with industry-leading IP providers to give our customers access to high-quality IPs. We are pleased to welcome Sofics to our IFS Accelerator IP Alliance”
Suk Lee, VP of Design Ecosystem Development at IFS
Director
“We are collaborating with industry-leading IP providers to give our customers access to high-quality IPs. We look forward to continued collaboration with Sofics to enable our customers to enjoy a proven selection of ESD protection IPs.”
Suk Lee, VP of Design Ecosystem Development at IFS
Director
“We look forward to working with Intel Foundry to support mutual customers with our proprietary ESD technology.”
Koen Verhaege, CEO of Sofics
Director
Further reading
Blog article “Optimized Local I/O ESD Protection in FinFET Technology for 2.5D and 3D hybrid integration“
Blog article “Optimized Local I/O ESD Protection for SerDes In Advanced SOI, BiCMOS and FinFET Technology“
Blog article “Optical communication also requires ESD protection“
Partnership announcement with Mixel MIPI
Lantiq licenses Sofics’ ESD solutions
Press announcement about our cooperation with DecaWave (now Qorvo)
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