For many applications IC designers cannot use the foundry provided GPIO’s or foundry ESD protection clamps.
For instance, excessive leakage prevents low-power circuits. High parasitic capacitance limits interface bandwidth.
Below are examples where Sofics IP can improve IC or interface performance.
Circuit design solutions for increased robustness and higher ratings
Clipping circuit
3.3V Signaling on a 40nm
1.8V I/O baseband chip
Last year, about 40% of new smartphones included Near Field Communication (NFC). According to analysts there are now 1 billion NFC enabled phones. Clearly, the use of NFC is ramping up because it can simplify aspects as diverse as communication, secure payments, user authentication, and retail loyalty programs for instance. Adding NFC functionality to an integrated circuit involves connecting the wireless interface pins to an antenna/coil. The voltage on those pads strongly depend on the distance between and alignment of transmit/read devices and the power of the transmitting device. The voltage can easily run above 10V, beyond the maximum tolerated voltage of the sensitive circuits.
Creating high voltage pins in advanced processes is an emerging topic receiving more and more attention. Often these stem from legacy requirements or from sensors and/or actuators that work on higher voltage levels then available in the process. Sofics engineers have an extensive track record in providing ESD solutions for these pins, with 5.5V solutions on a 55nm process or 12V solution on a standard 28nm process.
Sofics’ clipping circuit protects wireless interface circuits against excess voltage
3V IO in 28nm using 1.8V transistors – in mass production