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ESD clamps with low leakage

Sofics technology has been applied for many different applications. A number of applications require ESD solutions with (much) lower leakage compared to the conventional ESD clamps.
For instance, in IoT or medical circuits designers want to reduce total power consumption. In wireless applications, lower leakage improves the Q-factor for LNA circuits. Some high-impedance sensor interfaces need (ultra-low) leakage to ensure the bias levels are not affected.
Sofics ESD cells have orders of magnitude lower leakage (nano-Amps instead of micro-amps).
ESD-low-leakage

Examples in different processes

Examples for different process nodes are shown below. This is just a subset of cells proven on silicon and in mass production.

All cells can be ported to other processes. The actual numbers (ESD robustness, leakage, capacitance, area) may vary slightly, also depending on the circuit to be protected, process, voltage level.

Mature CMOS (0.5um to 180nm)

Process Pad ESD robustness Leakage
TSMC 180nm 1.8V rail >5 kV HBM <200 pA
TSMC 180nm 1.8V I/O >5 kV HBM <200 pA
TSMC 180nm 5V rail > 8 kV HBM < 5 nA
TSMC 180nm 5V I/O > 8 kV HBM < 5 nA
TSMC 180nm 7V I/O > 2 kV HBM < 50 nA
TowerSemi 350nm 4.5V rail > 8 kV HBM < 100 pA

Mainstream CMOS (130nm to 65nm)

Process pad ESD robustness Leakage
TSMC 130nm 1.0V I/O > 4 kV HBM < 50 pA
TSMC 130nm 1.0V rail > 3 kV HBM < 50 pA
TSMC 130nm 3.3V I/O > 3 kV HBM < 10 pA
UMC 130nm 1.2V I/O > 2 kV HBM < 10 nA
TSMC 90nm 1.8V rail > 2kV HBM < 0.5 nA
TSMC 65nm 1.0V I/O > 4 kV HBM < 1 nA
TSMC 65nm 1.2V rail > 2 kV HBM < 100 pA
GF 65nm 1.0V I/O > 2 kV HBM < 50 nA
GF 65nm 1.8V I/O > 3 kV HBM < 100 pA

Advanced CMOS (40nm to 22nm)

Process Pad ESD robustness Leakage
TSMC 40nm 0.9V rail > 2 kV HBM < 100 pA
TSMC 28nm 0.85V I/O > 2 kV HBM < 50 pA
TSMC 28nm 3.3V I/O > 200 V HBM < 40 pA

Comparing the foundry ESD solution to the Sofics approach on a 40nm CMOS process

SOI technology

Process Pad ESD robustness Leakage
GF 22FDX 1.2V rail > 2 kV HBM < 30 pA
GF 22FDX 1.2V I/O > 2 kV HBM < 50 pA
GF 22FDX 1.8V rail > 2 kV HBM < 50 pA
GF 22FDX 1.8V I/O > 2 kV HBM < 150 pA
GF 22FDX 3.3V rail > 5 kV HBM < 10 pA
GF 22FDX 3.3V I/O > 2 kV HBM < 500 pA

FinFET & FDSOI technology

BiCMOS technology

Process Pad ESD robustness Parasitic capacitance
TSMC 130nm 1.2V I/O > 4 kV HBM < 100 fF
TSMC 130nm 1.2V I/O OVT > 2 kV HBM < 50 fF
UMC 130nm 1.2V I/O > 2 kV HBM < 150 fF
TSMC 90nm 3.3V I/O > 2kV HBM < 100 fF
TSMC 65nm 1.8V I/O > 4 kV HBM < 100 fF
TSMC 65nm 1.0V I/O > 3 kV HBM < 70 fF
GF 65nm 1.2V I/O > 2 kV HBM < 50 fF
GF 65nm 3.3V I/O > 2 kV HBM < 50 fF

Other ways to search our IP

Check the benefits for each application type

Browse Sofics IP based on Process technology

Learn about the benefits of Sofics technology

Customer quotes

The implementation of TakeCharge will allow us to effectively manage ESD protection while continuing to quickly and cost-effectively deliver our next-generation, low-power programmable products to market.

Dr. Esmat Hamdy

senior vice president of technology and operations at Actel Corporation
We chose TakeCharge® technology for our FPGA product families as part of Altera’s commitment to deliver high-performance, cost-effective programmable products to our customers. TakeCharge® has allowed us to effectively manage both ESD protection and IO area.

Bradley Howe

vice president of IC Design at Altera
The TakeCharge Solution enables full flexibility in our designs in terms of specifications and area efficiency.

Michel De Mey

Senior Director of Hearing and Audio Solutions at AMIS
“A so comprehensive and detailed work-through of the ESD strategy and actual physical ESD triggering mechanisms has surpassed our expectations. The ESD support has helped increase our confidence to exceed our customer’s specialized requirements”

Erik Fossum Færevaag

Analog Manager, Energy Micro AS of Norway
“Thanks to our close collaboration with TSMC in the IP alliance, Sofics was able to transfer its proprietary ESD portfolio to the most advanced 5nm process technology”

Koen Verhaege

CEO of Sofics
“We have invested in bringing our proprietary ESD portfolio to the most advanced FinFET technology”

Koen Verhaege

CEO of Sofics
“We are delighted that our patent application for our unique clipping technology was granted. This PhyStar circuit will reduce cost and risk for many IC companies working on NFC designs”

Koen Verhaege

CEO of Sofics
“This defines one of our key roles in the IP eco-system: reducing time-to-market and optimizing customer profit by mitigating the risk, expenses and delays of ESD re-design”

Koen Verhaege

CEO of Sofics
“Fabless companies will always benefit from a shorter timeline and a lower cost combined with the confidence of a working solution.”

Koen Verhaege

CEO of Sofics
"Sofics and ICsense came up with a solution for us that works at high voltages and provides good ESD protection”

Pete Hughes

Vice President, Mobile, NVIDIA
“Sofics has been a strong supporter of the drive to improve the reliability of electronics, and has achieved several breakthroughs in ESD protection”

Noboru Shiono

Senior Manager of RCJ
“With the addition of  TakeCharge on-chip ESD protection design solutions to the UMC IP Alliance Program, UMC customers will have easy access to superior ESD design solutions from an industry wide  recognized leader in its field”

Ken Liou

director of the IP and Design Support Division at UMC
“Our alliance with UMC means that customers will achieve shorter design cycles for proven specialty solutions optimized with advanced ESD protection. Together, Sarnoff and UMC can better meet the specialized needs of our customers by bringing cost efficient, higher-quality solutions to market much faster.”

Koen Verhaege

CEO at Sofics
“Sofics combines IP in an advanced design flow with calculation and integration tools, and customized services. They complement the diverse Design Services offered by our portfolio of DCA partners,”

Tom Quan

Deputy Director at the Design Methodology and Service Marketing at TSMC
"Sofics is excited and honored to cooperate with TSMC. Our mission is to empower customers with advanced solutions and tools so they can independently perform successful ESD design, getting it right the first time, every time, regardless of the complexity of the process, application or innovation."

Koen verhaege

CEO at Sofics
“As a specialty foundry, it is important that we provide our fabless customers with a wide range of robust and efficient high-performance ESD protection solutions for all their logic and mixed-signal applications"

Dani Ashkenazi

General Manager CMOS Product Line at Tower Semiconductor
"Sofics has consistently been a reliable and expert ESD protection IP partner to the semiconductor industry, making them the natural choice as our partner for these demanding applications.”

Dani Ashkenazi

General Manager CMOS Product Line at Tower Semiconductor
“We are pleased that Tower Semiconductor selected our technology to provide a high quality ESD protection platform. TakeCharge ESD protection solutions are developed with scalability in mind, and thus can meet high-performance requirements, even up to 20kV HBM.”

Koen Verhaege

CEO at Sofics
“TakeCharge technology helps us reduce the die size of our chips for greater economy, while maintaining and ensuring ESD protection in all application areas including high speed”

Shigeo Koguchi

President and CEO of Toshiba’s Semiconductor Company
“We’ve had consistent success in designing more compact, higher-performance ESD protection into our ICs with TakeCharge. We will continue to collaborate with Sarnoff to develop solutions for our future processes such as 45nm and 32nm.”

Naoyuki Shigyo

Chief Specialist, System LSI Design Department of Toshiba’s Semiconductor Company
“We had faced many ESD problems which could not be solved easily two decades ago, especially on thin gate oxide process. Now, few ESD problems appear in our IC development, thanks to ESD protection technology that has been licensed from Sofics.”

Top-10 Semiconductor company

Director
“We are collaborating with industry-leading IP providers to give our customers access to high-quality IPs. We are pleased to welcome Sofics to our IFS Accelerator IP Alliance”

Suk Lee, VP of Design Ecosystem Development at IFS

Director
“We are collaborating with industry-leading IP providers to give our customers access to high-quality IPs. We look forward to continued collaboration with Sofics to enable our customers to enjoy a proven selection of ESD protection IPs.”

Suk Lee, VP of Design Ecosystem Development at IFS

Director
“We look forward to working with Intel Foundry to support mutual customers with our proprietary ESD technology.”

Koen Verhaege, CEO of Sofics

Director

Further reading

Blog articles where “low leakage ESD clamps” aspects are discussed.

Blog article “ESD protection for Internet-of-Things“

Blog article “Medical applications“