When the diode from I/O to Vdd causes problems Sofics proposes a local clamp approach
This can happen when the signal voltage on the I/O can go above the voltage on the reference Vdd domain.
Another typical reason is when designers need to use ‘open-drain’ communication lines like the I²C bus.
More recently it is also relevant when sub-domains on a SoC are powered down while the signals can still be applied.
Also in Space applications designers sometimes have a cold-spare chip that is not powered but still receives the I/O signals.