Mainstream CMOS (130nm to 55nm)

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Protecting chip interfaces against Electrostatic Discharge (ESD) needs dedicated attention. ESD remains an important reliability issue for semiconductor companies. ESD events can occur during several stages in the development, assembly and actual use of the ICs.

Sofics has verified its ESD protection clamps on many CMOS process nodes at several foundries and fabs. Integrating our solutions can enhance your competitive advantage.

Why IC designers need custom ESD cells

Most foundries running mainstream CMOS processes have a whole set of ESD protection clamps available. In these processes some of the conventional ESD approaches are still effective. There is also typical a full General Purpose I/O (GPIO) library available for free with ESD cells integrated.

However for novel applications, the IC designer can be constrained by the GPIO library. It could be that the parasitic capacitance of the integrated ESD protection clamps is excessive for high bandwidth interfaces (wired, wireless or optical). Or the leakage current of traditional ESD clamps prevents low-power applications like IoT or medical. Many applications also require much higher ESD robustness.

Why even designs in mainstream CMOS require custom ESD cells

Most foundries running mainstream CMOS processes have a whole set of ESD protection clamps available. In these processes some of the conventional ESD approaches are still effective. There is also typical a full General Purpose I/O (GPIO) library available for free with ESD cells integrated.

However frequently the IC designer is constraint by the GPIO library for novel applications. The parasitic capacitance of the integrated ESD protection clamps is too high for high bandwidth interfaces (wired, wireless or optical). The leakage current of traditional ESD clamps prevents low-power applications like IoT or medical. Many applications require much higher ESD robustness.

Sofics IP for Mainstream CMOS

Process technology covered

TSMC 130nm

TSMC 90nm

TSMC 65nm / 55nm

UMC 130nm

UMC 65nm

GlobalFoundries (IBM) 130nm

GlobalFoundries (Chartered) 65nm

Tower Semi 130nm

Lfoundry 110nm

HHGrace 110nm

XFab (Altis) 130nm

Several proprietary IDM fabs

Foundries covered

Key focus areas

A. High-Speed interfaces

Sofics IP is used in high bandwidth communication interfaces networks. These interfaces need ESD clamps with low parasitic capacitance. Sofics clamps provide standard ESD robustness and do not require a resistance in the signal path.

B. Beyond standard voltage levels

Our IP was used for sensor interfaces, battery connections and more. We have delivered solutions for high voltage tolerance (5V or higher) thanks to a flexible but deterministic solution set.

C. Battery powered applications

Customers have integrated Sofics ESD in IoT systems. The leakage of our ESD cells is 100x lower compared to conventional approach. Huge improvements can be made in stand-by, sleep, operational modes and during power-cycles. Sofics has solutions available for interfaces and rail clamps.

D. Harsh environments

Automotive applications typically require higher ESD robustness levels. Sofics ESD technology can be easily scaled to reach higher HBM and CDM protection levels. In some cases the on-chip ESD cells are adapted to sustain contact discharge 8kV IEC 61000-4-2.

E. Radiation hard and cold-spare

Integrated circuits used in space, nuclear physics research or several medical applications require a higher tolerance against radiation. The conventional I/O circuits and ESD devices degrade under this kind of stress. Fortunately, Sofics has proven solutions.

IC products from our customers

Our customers have created amazing products even on mainstream CMOS technology. Examples include high-speed interfaces for consumer, datacenter applications, wireless IoT, bluetooth, wifi circuits, low-power Internet of Things devices and TCON (Timing controller) chips in flat panel displays. Several of our IDM customers have used Sofics IP for Display Drivers for these same displays. The mainstream CMOS processes on several foundries have been used for SIM/smartcard chips. A higher ESD robustness is required for those chips.