Mainstream CMOS (130nm to 55nm)

Protecting chip interfaces against Electrostatic Discharge (ESD) needs dedicated attention. ESD remains an important reliability issue for semiconductor companies. ESD events can occur during several stages in the development, assembly and actual use of the ICs.

Sofics has verified its ESD protection clamps on many CMOS process nodes at several foundries and fabs. Integrating our solutions can enhance your competitive advantage.

Why IC designers need custom ESD cells

Most foundries running mainstream CMOS processes have a whole set of ESD protection clamps available. In these processes some of the conventional ESD approaches are still effective. There is also typical a full General Purpose I/O (GPIO) library available for free with ESD cells integrated.

However for novel applications, the IC designer can be constrained by the GPIO library. It could be that the parasitic capacitance of the integrated ESD protection clamps is excessive for high bandwidth interfaces (wired, wireless or optical). Or the leakage current of traditional ESD clamps prevents low-power applications like IoT or medical. Many applications also require much higher ESD robustness.

Why even designs in mainstream CMOS require custom ESD cells

However frequently the IC designer is constraint by the GPIO library for novel applications. The parasitic capacitance of the integrated ESD protection clamps is too high for high bandwidth interfaces (wired, wireless or optical). The leakage current of traditional ESD clamps prevents low-power applications like IoT or medical. Many applications require much higher ESD robustness.

Sofics IP for Mainstream CMOS

Process technology covered

TSMC 130nm

TSMC 90nm

TSMC 65nm / 55nm

UMC 130nm

UMC 65nm

GlobalFoundries (IBM) 130nm

GlobalFoundries (Chartered) 65nm

Tower Semi 130nm

Lfoundry 110nm

HHGrace 110nm

XFab (Altis) 130nm

Several proprietary IDM fabs

Foundries covered

Fujitsu

IDM fabs

Key focus areas

A. High-Speed interfaces

Sofics IP is used in high bandwidth communication interfaces networks. These interfaces need ESD clamps with low parasitic capacitance. Sofics clamps provide standard ESD robustness and do not require a resistance in the signal path.

ESD with low capacitance

B. Beyond standard voltage levels

Our IP was used for sensor interfaces, battery connections and more. We have delivered solutions for high voltage tolerance (5V or higher) thanks to a flexible but deterministic solution set.

High voltage tolerant ESD

C. Battery powered applications

Customers have integrated Sofics ESD in IoT systems. The leakage of our ESD cells is 100x lower compared to conventional approach. Huge improvements can be made in stand-by, sleep, operational modes and during power-cycles. Sofics has solutions available for interfaces and rail clamps.

Low leakage ESD

D. Harsh environments

Automotive applications typically require higher ESD robustness levels. Sofics ESD technology can be easily scaled to reach higher HBM and CDM protection levels. In some cases the on-chip ESD cells are adapted to sustain contact discharge 8kV IEC 61000-4-2.

Clamps with high ESD robustness

E. Radiation hard and cold-spare

Integrated circuits used in space, nuclear physics research or several medical applications require a higher tolerance against radiation. The conventional I/O circuits and ESD devices degrade under this kind of stress. Fortunately, Sofics has proven solutions.

Rad-hard ESD clamps

IC products from our customers

Our customers have created amazing products even on mainstream CMOS technology. Examples include high-speed interfaces for consumer, datacenter applications, wireless IoT, bluetooth, wifi circuits, low-power Internet of Things devices and TCON (Timing controller) chips in flat panel displays. Several of our IDM customers have used Sofics IP for Display Drivers for these same displays. The mainstream CMOS processes on several foundries have been used for SIM/smartcard chips. A higher ESD robustness is required for those chips.

We chose the TakeCharge solution because it provides state-of-the-art ESD protection while ensuring ‘first time right’ design

Dr. Esmat Hamdy

senior vice president of technology and operations at Actel Corporation

The implementation of TakeCharge will allow us to effectively manage ESD protection while continuing to quickly and cost-effectively deliver our next-generation, low-power programmable products to market.

Dr. Esmat Hamdy

senior vice president of technology and operations at Actel Corporation

We chose TakeCharge® technology for our FPGA product families as part of Altera’s commitment to deliver high-performance, cost-effective programmable products to our customers. TakeCharge® has allowed us to effectively manage both ESD protection and IO area.

Bradley Howe

vice president of IC Design at Altera

Specialized ESD design solutions within a very short turnaround time. They truly demonstrated first-time-right delivery capabilities.

Michel De Mey

Senior Director of Hearing and Audio Solutions at AMIS

Easy-to-use, easy-to-integrate TakeCharge ESD protection solution so we can focus on bringing our cutting-edge industry standard products to customers quickly and cost effectively.

Michel De Mey

Senior Director of Hearing and Audio Solutions at AMIS

The TakeCharge Solution enables full flexibility in our designs in terms of specifications and area efficiency.

Michel De Mey

Senior Director of Hearing and Audio Solutions at AMIS

“Our goal was to boost the robustness of our ESD/EOS protection without making extensive changes to our design masks, so we decided to engage experts in the field. Sofics optimized our product in less than two weeks. Everything worked perfectly. In tests of the chips we found no failure far beyond the required maximum stress voltage, which means there’s headroom even above that.”

Dr. Steffen Buschbeck

Anvo-Systems project manager

“A so comprehensive and detailed work-through of the ESD strategy and actual physical ESD triggering mechanisms has surpassed our expectations. The ESD support has helped increase our confidence to exceed our customer’s specialized requirements”

Erik Fossum Færevaag

Analog Manager, Energy Micro AS of Norway

“Adding Sofics’ ESD protection and other I/Os into the target options will enable solutions to be found and implemented much more rapidly.”

Sowmyan Rajagopalan

Thalia Design Automation CEO

“To ensure good signal integrity, the MIPI PHY interfaces need to be paired with analog I/Os with low parasitic capacitance.”

Koen Verhaege

CEO of Sofics

“We are delighted that our patent application for our unique clipping technology was granted. This PhyStar circuit will reduce cost and risk for many IC companies working on NFC designs”

Koen Verhaege

CEO of Sofics

“This defines one of our key roles in the IP eco-system: reducing time-to-market and optimizing customer profit by mitigating the risk, expenses and delays of ESD re-design”

Koen Verhaege

CEO of Sofics

“Fabless companies will always benefit from a shorter timeline and a lower cost combined with the confidence of a working solution.”

Koen Verhaege

CEO of Sofics

“With Sofics’ technology, Lantiq’s 130nm and 65nm HP products are more economic for a wide range of chip-hostile environments”

Christoph von Schierstädt

Lantiq Communications Manager

“Sofics’ ESD solutions together with Lantiq’s best-in-class Telecom products thus create a triple-win solution for Sofics, Lantiq and its customers”

Christoph von Schierstädt

Lantiq Communications Manager

“Sofics delivered a customized ESD solution in less than a week”

William McFadden

VP Operations at DecaWave

“TakeCharge was also far more cost-effective than other approaches to ESD protection”

William McFadden

VP Operations at DecaWave

“When we started development of our newest ICs for SIMs and smartcards we selected Sofics to develop robust, full-chip ESD protection to meet reliability requirements far beyond typical standards, in a foundry process that was new to both of us”

Christian Dupuy

COO of StarChip

“Sofics provided a solution that worked perfectly the first time. There was no need for re-spins, no significant increase in silicon real estate, and no ESD masks or other process extras. This minimized our development time and wafer costs.”

Christian Dupuy

COO of StarChip

“We were able to meet StarChip’s requirements and timeline because the TakeCharge portfolio is highly portable across foundries and easily adapts to provide higher protection and meet specialty ESD requirements”

Koen Verhaege

CEO at Sofics

“We significantly reduced our customer’s cost of development and design, and enabled faster time-to-market.”

Koen Verhaege

CEO at Sofics

“Sofics has been a strong supporter of the drive to improve the reliability of electronics, and has achieved several breakthroughs in ESD protection”

Noboru Shiono

Senior Manager of RCJ

“With the addition of TakeCharge on-chip ESD protection design solutions to the UMC IP Alliance Program, UMC customers will have easy access to superior ESD design solutions from an industry wide recognized leader in its field”

Ken Liou

director of the IP and Design Support Division at UMC

“Our alliance with UMC means that customers will achieve shorter design cycles for proven specialty solutions optimized with advanced ESD protection. Together, Sarnoff and UMC can better meet the specialized needs of our customers by bringing cost efficient, higher-quality solutions to market much faster.”

Koen Verhaege

CEO at Sofics

“Sofics combines IP in an advanced design flow with calculation and integration tools, and customized services. They complement the diverse Design Services offered by our portfolio of DCA partners,”

Tom Quan

Deputy Director at the Design Methodology and Service Marketing at TSMC

"Sofics is excited and honored to cooperate with TSMC. Our mission is to empower customers with advanced solutions and tools so they can independently perform successful ESD design, getting it right the first time, every time, regardless of the complexity of the process, application or innovation."

Koen verhaege

CEO at Sofics

“Using Sofics' ESD solutions we significantly lower our technical and business risks and expenses."

Kenji Numata

Senior Manager, System LSI Design Department of Toshiba’s Semiconductor Company

"This makes TakeCharge our standard choice solution for ESD protection, and we offer its unique benefits to our customers."

Kenji Numata

Senior Manager, System LSI Design Department of Toshiba’s Semiconductor Company

"Reuse of TakeCharge IP in Toshiba’s 180nm to 65nm ASIC products has consistently resulted in robust Charged Device Model (CDM), Human Body Model (HBM) and Machine Model (MM) performance.”

Kenji Numata

Senior Manager, System LSI Design Department of Toshiba’s Semiconductor Company

“We are dedicated to Toshiba’s business success in 32nm and beyond, and in the arena of COT and foundry services. The expanded licensing agreement will enable us to further strengthen the technical collaboration with Toshiba’s ESD team in the years to come.”

Koen Verhaege

CEO at Sofics

“The TakeCharge Design Kit enabled RedMere to quickly and economically increase our IC ESD performance to a new HDMI industry standard of 8kV HBM without compromising the stringent operation requirements of a 3.4Gbps data channel. They truly demonstrated the ease-of-use and scalability of their solutions”.

Peter Smyth

CEO of RedMere Technology

“RedMere Technology’s selection of TakeCharge to aid in a successful first to-market introduction of their HDMI application proves the trust semiconductor companies have placed in the effectiveness of i-our ESD solutions"

Koen Verhaege

CEO at Sofics

“TakeCharge enables design engineers to access the most advanced on-chip, extreme low-capacity and area efficient ESD solutions."

Koen Verhaege

CEO at Sofics

“As a specialty foundry, it is important that we provide our fabless customers with a wide range of robust and efficient high-performance ESD protection solutions for all their logic and mixed-signal applications"

Dani Ashkenazi

General Manager CMOS Product Line at Tower Semiconductor

"Sofics has consistently been a reliable and expert ESD protection IP partner to the semiconductor industry, making them the natural choice as our partner for these demanding applications.”

Dani Ashkenazi

General Manager CMOS Product Line at Tower Semiconductor

“We are pleased that Tower Semiconductor selected our technology to provide a high quality ESD protection platform. TakeCharge ESD protection solutions are developed with scalability in mind, and thus can meet high-performance requirements, even up to 20kV HBM.”

Koen Verhaege

CEO at Sofics

“Fujitsu selected TakeCharge to help continue our tradition of providing customers with highly reliable high-performance products and services based on powerful technologies,”

Shoji Ichino

general manager, Technology Development Division, Electronic Devices Business Unit of Fujitsu Limited.

“System manufacturers are increasingly asking IC suppliers for CDM-protected devices. Based on our previous success with TakeCharge CDM protection solution will help us meet that challenge and further solidify Toshiba's competitive position.”

Naoyuki Shigyo

chief specialist in the Analog CAD Engineering Department of Toshiba’s Semiconductor Company

Toshiba has been using technology based on TakeCharge to protect its CMOS ICs from Human Body Model (HBM) and Machine Model (MM) ESD since 2000. The approach has been applied to high-volume 0.18μm, 0.13μm, and 90nm products.

Naoyuki Shigyo

chief specialist in the Analog CAD Engineering Department of Toshiba’s Semiconductor Company

“TakeCharge technology can reduce the capacitance of the input and output (I/O) pins of HV-CMOS IC’s. Therefore, its application can reduce the power required to drive the data bus”

Fumihisa Nakamura

Category Director, Display Driver and PDP, System LSI Division of Matsushita Semiconductor Company.

“TakeCharge technology helps us reduce the die size of our chips for greater economy, while maintaining and ensuring ESD protection in all application areas including high speed”

Shigeo Koguchi

President and CEO of Toshiba’s Semiconductor Company

“We’ve had consistent success in designing more compact, higher-performance ESD protection into our ICs with TakeCharge. We will continue to collaborate with Sarnoff to develop solutions for our future processes such as 45nm and 32nm.”

Naoyuki Shigyo

Chief Specialist, System LSI Design Department of Toshiba’s Semiconductor Company

“We had faced many ESD problems which could not be solved easily two decades ago, especially on thin gate oxide process. Now, few ESD problems appear in our IC development, thanks to ESD protection technology that has been licensed from Sofics.”

Top-10 Semiconductor company

Director